Re: X on 10.0 RC1 is unusable on my laptop

[Brett Lymn <blymn%internode.on.net@localhost>]

On Sun, Nov 26, 2023 at 03:46:18PM +0000, Mike Pumford wrote:
> 
> From the reading of the code and commit comments I came away with the
> impression that they couldn't be moved in the 5.6 codebase due to needing
> different trigger points for the workround and also the workround engine
> couldn't handle writes to some of the registers without some structural
> changes.
> 

OK - here are the diffs, I just apply the gen 8 work arounds, there is a
couple of complaints but they don't seem to break anything but,
likewise, they may be pointless...

-- 
Brett Lymn
--
Sent from my NetBSD device.

"We are were wolves",
"You mean werewolves?",
"No we were wolves, now we are something else entirely",
"Oh"

Index: dist/drm/i915/i915_pci.c
===================================================================
RCS file: /cvsroot/src/sys/external/bsd/drm2/dist/drm/i915/i915_pci.c,v
retrieving revision 1.4
diff -u -r1.4 i915_pci.c
--- dist/drm/i915/i915_pci.c	19 Dec 2021 01:44:49 -0000	1.4
+++ dist/drm/i915/i915_pci.c	27 Nov 2023 05:59:00 -0000
@@ -442,7 +442,7 @@
 	.has_rc6 = 1, \
 	.has_rc6p = 1, \
 	.has_rps = true, \
-	.ppgtt_type = INTEL_PPGTT_FULL, \
+	.ppgtt_type = INTEL_PPGTT_ALIASING, \
 	.ppgtt_size = 31, \
 	IVB_PIPE_OFFSETS, \
 	IVB_CURSOR_OFFSETS, \
@@ -499,7 +499,7 @@
 	.has_rps = true,
 	.display.has_gmch = 1,
 	.display.has_hotplug = 1,
-	.ppgtt_type = INTEL_PPGTT_FULL,
+	.ppgtt_type = INTEL_PPGTT_ALIASING,
 	.ppgtt_size = 31,
 	.has_snoop = true,
 	.has_coherent_ggtt = false,
Index: dist/drm/i915/i915_reg.h
===================================================================
RCS file: /cvsroot/src/sys/external/bsd/drm2/dist/drm/i915/i915_reg.h,v
retrieving revision 1.19
diff -u -r1.19 i915_reg.h
--- dist/drm/i915/i915_reg.h	19 Dec 2021 12:24:36 -0000	1.19
+++ dist/drm/i915/i915_reg.h	27 Nov 2023 05:59:01 -0000
@@ -7775,6 +7775,9 @@
 #define   MASK_WAKEMEM			(1 << 13)
 #define   CNL_DDI_CLOCK_REG_ACCESS_ON	(1 << 7)
 
+#define BASIL_SAGV			_MMIO(0x46434)
+#define SAGV_DISABLE			(15 << 24)
+
 #define SKL_DFSM			_MMIO(0x51000)
 #define   SKL_DFSM_DISPLAY_PM_DISABLE	(1 << 27)
 #define   SKL_DFSM_DISPLAY_HDCP_DISABLE	(1 << 25)
Index: dist/drm/i915/gt/intel_workarounds.c
===================================================================
RCS file: /cvsroot/src/sys/external/bsd/drm2/dist/drm/i915/gt/intel_workarounds.c,v
retrieving revision 1.3
diff -u -r1.3 intel_workarounds.c
--- dist/drm/i915/gt/intel_workarounds.c	19 Dec 2021 11:49:11 -0000	1.3
+++ dist/drm/i915/gt/intel_workarounds.c	27 Nov 2023 05:59:02 -0000
@@ -351,7 +351,7 @@
 			  HDC_FORCE_NON_COHERENT);
 
 	/* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl,cfl */
-	if (IS_SKYLAKE(i915) || IS_KABYLAKE(i915) || IS_COFFEELAKE(i915))
+	if (IS_SKYLAKE(i915) || IS_KABYLAKE(i915) || IS_COFFEELAKE(i915) || (INTEL_GEN(i915) == 7))
 		WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
 				  GEN8_SAMPLER_POWER_BYPASS_DIS);
 
@@ -634,6 +634,8 @@
 		chv_ctx_workarounds_init(engine, wal);
 	else if (IS_BROADWELL(i915))
 		bdw_ctx_workarounds_init(engine, wal);
+	else if (INTEL_GEN(i915) == 7)
+		skl_ctx_workarounds_init(engine, wal);
 	else if (INTEL_GEN(i915) < 8)
 		return;
 	else
@@ -964,6 +966,8 @@
 		bxt_gt_workarounds_init(i915, wal);
 	else if (IS_SKYLAKE(i915))
 		skl_gt_workarounds_init(i915, wal);
+	else if (INTEL_GEN(i915) == 7)
+		skl_gt_workarounds_init(i915, wal);
 	else if (INTEL_GEN(i915) <= 8)
 		return;
 	else
@@ -1288,7 +1292,7 @@
 		kbl_whitelist_build(engine);
 	else if (IS_BROXTON(i915))
 		bxt_whitelist_build(engine);
-	else if (IS_SKYLAKE(i915))
+	else if (IS_SKYLAKE(i915) || (INTEL_GEN(i915) == 7))
 		skl_whitelist_build(engine);
 	else if (INTEL_GEN(i915) <= 8)
 		return;
@@ -1326,6 +1330,9 @@
 {
 	struct drm_i915_private *i915 = engine->i915;
 
+	wa_write_or(wal,
+		    BASIL_SAGV, SAGV_DISABLE);
+
 	if (IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) {
 		/* Wa_1606700617:tgl */
 		wa_masked_en(wal,
@@ -1426,7 +1433,7 @@
 			     GEN9_FFSC_PERCTX_PREEMPT_CTRL);
 	}
 
-	if (IS_SKYLAKE(i915) || IS_KABYLAKE(i915) || IS_COFFEELAKE(i915)) {
+	if (IS_SKYLAKE(i915) || IS_KABYLAKE(i915) || IS_COFFEELAKE(i915) || (INTEL_GEN(i915) == 7)) {
 		/* WaEnableGapsTsvCreditFix:skl,kbl,cfl */
 		wa_write_or(wal,
 			    GEN8_GARBCNTL,
@@ -1471,6 +1478,9 @@
 {
 	struct drm_i915_private *i915 = engine->i915;
 
+	wa_write_or(wal,
+		    BASIL_SAGV, SAGV_DISABLE);
+
 	/* WaKBLVECSSemaphoreWaitPoll:kbl */
 	if (IS_KBL_REVID(i915, KBL_REVID_A0, KBL_REVID_E0)) {
 		wa_write(wal,