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Re: NetBSD hardclock overhead growth

2015-08-28 5:21 GMT+02:00 Michael L. Hitch <mhitch%netbsd.org@localhost>:
>>> The KA48 System Board Specification says that you can write all bank
>>> enable bits, but reading them back will only yield the factory-enabled
>>> ("lasar [sic!] fused") ones set to 1.
>>> On the KA660, it seems this is not the case (also implied by the
>>> statement that the firmware writes the bank enable bits).
>>  I'll try this on my second VLC, which showed one bank missing.
>   Looks like the Specification is correct.

Then if we decided to write 0xff to BEHR on the VLC, there could be no
common cache enable function. KA660's routine should be no harm
however (hopefully).

I wonder where our code for the KA660 comes from, which tests working
banks by enabling each bank individually, writing two bit patterns
into cache data and checking if reads reflect them.
As the firmware already enables the cache, I can try to figure out the
"official" procedure from disassembling the ROM... Let's see if an
"EXAMINE /INSTRUCTION" over the whole ROM address space works (and how
many hours it will take). :)


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