Re: Silly question - a further one : TLB flush

[Vincent <10.50%free.fr@localhost>]

Manuel,
> Simplicity in the design of the chip (and so in silicium surface)

This, IMHO, has never been an Intel goal (Motorola always had better 
orthogonal design, starting with the 68000).

> You have to have a 64bit tlb anyway for support of the 64bit mode;
> so in 32bit mode it's much simpler, from a electronic design POW, to
> just set the 32 upper bits to 0 on data path entry of the TBL than
> to have internals of the TLB work in a different way (basically requiring
> every TLB registers to be dual-mode, as well as the lookup and eviction
> logics). This would be a quite high cost on the silicium, maybe near of

Not really. This is only a matter of multiplexing a32-63 according to a 
mode bit. Example for the comparator :

TLB (Low) ------ CMP ---> result(1)
                  ^
                  |
A0 - A31  --------+
                  |
                  V
A32- A63  ------>MUX <---- 32/64 BIT-MODE
                  |
                  V
TLB (High) ----->CMP ---> result (2)



> doubing the on-die size of the TLB. This would also be a cost in 
timing, as
> you're adding extra gates in the critical path.

True, there is one extra stage, but I don't think it really matters much.

Well, Manuel, on peut poursuivre par mail, or on the regional list, 
because I don't think this is kernel relevant anyhow ;)

Vincent