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Re: Silly question - a further one : TLB flush

On Sun, Sep 07, 2008 at 01:23:56PM +0200, Vincent wrote:
> [...]
> >Note that increasing the size and numbers of registers does have 
> >penalties, as you have to store them somewhere (stack) when context 
> >switching. This penalizes microkernels based OS, since you are 
> >frequently switching, compared to bigger, monolith ones.
> Agreed. And I guess that with 64-bit adresses, the TLB is somewhat 
> smaller, since a cache line would hold only half of its 32-bit contents.

This I'm not sure. I guess the CPU is using 64bit data path internally,
even in 32bit mode, so the number of entries in the TLB is probably
the same in 32 and 64bit modes. Using 2 different TLB formats would
make things more complext for no real gain.

Manuel Bouyer <>
     NetBSD: 26 ans d'experience feront toujours la difference

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