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Re: Silly question - a further one : TLB flush

Manuel Bouyer wrote:
On Sun, Sep 07, 2008 at 02:31:16PM +0200, Vincent wrote:
Simplicity in the design of the chip (and so in silicium surface)
You have to have a 64bit tlb anyway for support of the 64bit mode;
so in 32bit mode it's much simpler, from a electronic design POW, to
just set the 32 upper bits to 0 on data path entry of the TBL than
to have internals of the TLB work in a different way (basically requiring
every TLB registers to be dual-mode, as well as the lookup and eviction
logics). This would be a quite high cost on the silicium, maybe near of
doubing the on-die size of the TLB. This would also be a cost in timing, as
you're adding extra gates in the critical path.

@Vincent: I am not sure that it requires the TLB size to be doubled though. Most of the x86_64 CPUs are currently using 48 bits for their address space, separated in two "virtual" parts (0 => 2^47, and (2^64 - 2^47) => 2^64), with the assumption that bits [63:48] have the same value as bit 47 (if not, the CPU raises an exception). This makes plenty of space anyway :)

Jean-Yves Migeon

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