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Re: Silly question - a further one : TLB flush
Jean-Yves Migeon a écrit :
Could you provide me with a link to this article please?
The article may be fetched here:
For i386, netbsd uses a 3GB/1GB memory split and a flat address space
(the descriptor table is loaded with a segment starting at address 0 and
ending at the 4GB boundary). As a consequence, the MMU contains both
user and kernel mappings, which do not require a TLB flush when
Ok, that's what Windows does.
What you are describing happens for amd64 OSs running under Xen though.
x86_64 removed the concept of segmentation, and left two rings, a
privileged and unprivileged one, while i386 provides 4 ring levels.
So with x86_64 we are reverting to the 68x (;)) two levels I'm familiar
with: user and supervisor. Xen works as a virtual machine, if I am not
Note that increasing the size and numbers of registers does have
penalties, as you have to store them somewhere (stack) when context
switching. This penalizes microkernels based OS, since you are
frequently switching, compared to bigger, monolith ones.
Agreed. And I guess that with 64-bit adresses, the TLB is somewhat
smaller, since a cache line would hold only half of its 32-bit contents.
So there are pros and cons, it's worth trying anyway — as soon the new
MacBooks are unleashed, I'll have a look.
Merci, en tout cas, et bonne fin de dimanche !
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