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Re: physical address space management
On Wed, Apr 02, 2008 at 09:23:35PM -0500, David Young wrote:
> On Fri, Mar 28, 2008 at 06:19:24PM -0400, Nathan J. Williams wrote:
> > [..] How does this interact with architectures where
> > cacheability et al are MMU-level mapping properties?
> pmap(9) and bus_dma(9) must respect the protection and properties
> of any physical region that they map. Routines such as pmap_enter(),
> pmap_kenter_pa(), pmap_zero_page(), pmap_copy_page(), and bus_dmamem_map()
> need to make appropriate calls to the physmem manager.
On machines where all the properties you describe are just difference in
the (IO)MMU mappings, it is most likely that the total physical memory
is pretty uniform, attribute wise. So the pmap operation will request the
memory area from the physmem manager (like it requests it from uvm
right now), and create proper mappings for the needed attributes.
Not much of a change on those archs.
At least that is how I understand the proposal so far.
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