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Re: physical address space management
On Friday 28 March 2008 21:03:29 David Young wrote:
> enum pmem_props { /* hardware implementation */
> PMEM_P_WTHRU = 0x01 /* MTRR */
> , PMEM_P_WBACK = 0x02 /* MTRR */
> , PMEM_P_WCOMB = 0x04 /* MTRR */
> , PMEM_P_UNCACHED = 0x08 /* MTRR, AMD Elan SC520 PAR */
> , PMEM_P_PREFETCH = 0x10 /* PCI bus bridge */
> };
>
> enum pmem_type {
> , PMEM_T_RAM = 0x01
> , PMEM_T_ROM = 0x02
> , PMEM_T_PCI = 0x04
> };
There are additional properties you may wish to account for, such as
databus width and address modifiers (e.g. VMEbus).
How would you represent endian issues? For example a PCIbus hooked up to
a big-endian CPU?
Cheers, Steve
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