Re: physical address space management

[David Young <dyoung%pobox.com@localhost>]

On Fri, Mar 28, 2008 at 06:19:24PM -0400, Nathan J. Williams wrote:
> David Young <dyoung%pobox.com@localhost> writes:
> 
> >         * abstract cache-control, execute- and write-protection features
> >           of x86 MTRR, AMD Elan SC520, et cetera
> 
> These are systems where there's a comparatively low-level setting of
> properties on regions. How does this interact with architectures where
> cacheability et al are MMU-level mapping properties?

pmap(9) and bus_dma(9) must respect the protection and properties
of any physical region that they map.  Routines such as pmap_enter(),
pmap_kenter_pa(), pmap_zero_page(), pmap_copy_page(), and bus_dmamem_map()
need to make appropriate calls to the physmem manager.

On reflection, I have decided that the API needs the notions of
"exclusive/mandatory" and "advisory" properties and protection.  One user
of a physical region may advise that a region should be cacheable.
Another user may mandate that the same region should be uncached.
The mandate trumps the advice, and the region will not be cached.  If a
third user tries to mandate that the region is cached, then the operation
fails.  Another user may exclude writers from a region with pmem(9).
A second user may advise pmem(9) that it will write the same region;
the second user's pmem(9) operation will fail with EPERM.

Dave

-- 
David Young             OJC Technologies
dyoung%ojctech.com@localhost      Urbana, IL * (217) 278-3933 ext 24