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Re: physical address space management

David Young <> writes:

>         * abstract cache-control, execute- and write-protection features
>           of x86 MTRR, AMD Elan SC520, et cetera

These are systems where there's a comparatively low-level setting of
properties on regions. How does this interact with architectures where
cacheability et al are MMU-level mapping properties?

        - Nathan

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