Re: CardBus testers needed

[Thor Lancelot Simon <tls%panix.com@localhost>]

On Thu, Mar 11, 2010 at 11:56:12AM -0600, David Young wrote:
> 
> Finally, we have the PCI-CardBus bridge.
> 
> There are I/O- and memory-space windows on each PCI-* bridge.  They tell
> which addresses are on the secondary side of the bridge.  (The secondary
> side is the side that is farther from the chipset.  The primary side
> is nearer to the chipset.)  When a bridge sees a transaction address
> on its primary side that is in the applicable window, it forwards the
> transaction to its secondary side.
> 
> I'm concerned that your CardBus bridge's memory-mapped registers are at
> [0xcffe0000, 0xcfffffff],

I suspect these are the default, uninitialized values of the registers
controlling the mapping; or otherwise, junk values which weren't
initialized.

I don't know about the last parallel-PCI specs, but there were certainly
intermediate versions of the spec which many vendors read as requiring
merely that the BIOS configure devices actually required in order to boot,
in the as-shipped system configuration.  The result was that bridges on
add-in cards would often not be configured at all, or be configured ONLY
if a device behind the bridge somehow got a boot ROM mapped in.

You don't want to know how many times I've seen this with PCI-PCI
bridges mounted on a card, in fact.  I wouldn't be surprised at all to
see a vendor interpret the same spec such that they didn't have to
set up the mappings for the PCI-CardBus bridge and punt the whole thing
to Windows to handle after booting from a device on one of the BIOS-
configured buses.

Thor