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Re: CardBus testers needed
>>>>> "David" == David Young <dyoung%pobox.com@localhost> writes:
David> Please send 'pcictl pci0 dump -d 20 -f 4'.
>>
>> Attached:
David> Thanks. Send pcictl output for the CardBus bridge again,
David> too, and the host bridge.
According to my dmesg output (excerpt):
pci0 at mainbus0 bus 0: configuration mode 1
[...]
ppb2 at pci0 dev 20 function 4: ATI Technologies SB600 PCI to PCI Bridge
(rev. 0x00)
pci3 at ppb2 bus 3
pci3: i/o space, memory space enabled
cbb0 at pci3 dev 5 function 0: ENE Technology CB1410 CardBus Controller (rev.
0x01)
[...]
cbb0: cacheline 0x10 lattimer 0x40
cbb0: bhlc 0x24010
cbb0: interrupting at ioapic0 pin 20
cardslot0 at cbb0
cardbus0 at cardslot0: bus 4
pcmcia0 at cardslot0
That should be:
The host bridge (Didn't we have this already?):
$ pcictl pci0 dump -d 20 -f 4
PCI configuration registers:
Common header:
0x00: 0x43841002 0x02a00107 0x06040100 0x00814000
Vendor Name: ATI Technologies (0x1002)
Device Name: SB600 PCI to PCI Bridge (0x4384)
Command register: 0x0107
I/O space accesses: on
Memory space accesses: on
Bus mastering: on
Special cycles: off
MWI transactions: off
Palette snooping: off
Parity error checking: off
Address/data stepping: off
System error (SERR): on
Fast back-to-back transactions: off
Interrupt disable: off
Status register: 0x02a0
Capability List support: off
66 MHz capable: on
User Definable Features (UDF) support: off
Fast back-to-back capable: on
Data parity error detected: off
DEVSEL timing: medium (0x1)
Slave signaled Target Abort: off
Master received Target Abort: off
Master received Master Abort: off
Asserted System Error (SERR): off
Parity error detected: off
Class Name: bridge (0x06)
Subclass Name: PCI (0x04)
Interface: 0x01
Revision ID: 0x00
BIST: 0x00
Header Type: 0x01+multifunction (0x81)
Latency Timer: 0x40
Cache Line Size: 0x00
Type 1 (PCI-PCI bridge) header:
0x10: 0x00000000 0x00000000 0x40040300 0x6280e0c0
0x20: 0xfeb0fe30 0xfcf0fb00 0x00000000 0x00000000
0x30: 0x00000000 0x00000000 0x00000000 0x00030000
Base address register at 0x10
not implemented(?)
Base address register at 0x14
not implemented(?)
Primary bus number: 0x00
Secondary bus number: 0x03
Subordinate bus number: 0x04
Secondary bus latency timer: 0x40
Secondary status register: 0x6280
66 MHz capable: off
User Definable Features (UDF) support: off
Fast back-to-back capable: on
Data parity error detected: off
DEVSEL timing: medium (0x1)
Signalled target abort: off
Received target abort: off
Received master abort: on
Received system error: on
Detected parity error: off
I/O region:
base register: 0xc0
limit register: 0xe0
base upper 16 bits register: 0x0000
limit upper 16 bits register: 0x0000
Memory region:
base register: 0xfe30
limit register: 0xfeb0
Prefetchable memory region:
base register: 0xfb00
limit register: 0xfcf0
base upper 32 bits register: 0x00000000
limit upper 32 bits register: 0x00000000
Reserved @ 0x34: 0x00000000
Expansion ROM Base Address: 0x00000000
Interrupt line: 0x00
Interrupt pin: 0x00 (none)
Bridge control register: 0x0003
Parity error response: on
Secondary SERR forwarding: on
ISA enable: off
VGA enable: off
Master abort reporting: off
Secondary bus reset: off
Fast back-to-back capable: off
Device-dependent header:
0x40: 0xff3c0026 0x00000000 0xd13f0f0c 0x00000100
0x50: 0x00000001 0xa8030008 0x00000000 0xffff0085
0x60: 0x00170eca 0x0010d8ba 0x00000000 0x00000000
0x70: 0x00000000 0x00000000 0x00000000 0x00000000
0x80: 0x00000000 0x00000000 0x00000000 0x00000000
0x90: 0x00000000 0x00000000 0x00000000 0x00000000
0xa0: 0x00000000 0x00000000 0x00000000 0x00000000
0xb0: 0x00000000 0x00000000 0x00000000 0x00000000
0xc0: 0x00000000 0x00000000 0x00000000 0x00000000
0xd0: 0x00000000 0x00000000 0x00000000 0x06020001
0xe0: 0x00800000 0x00000000 0x00000000 0x00000000
0xf0: 0x00000000 0x00000000 0x00000000 0x00000000
For the CardBis bridge:
$ pcictl pci3 dump -d 5 -f 0
PCI configuration registers:
Common header:
0x00: 0x14101524 0xc2100147 0x06070001 0x00024010
Vendor Name: ENE Technology (0x1524)
Device Name: CB1410 CardBus Controller (0x1410)
Command register: 0x0147
I/O space accesses: on
Memory space accesses: on
Bus mastering: on
Special cycles: off
MWI transactions: off
Palette snooping: off
Parity error checking: on
Address/data stepping: off
System error (SERR): on
Fast back-to-back transactions: off
Interrupt disable: off
Status register: 0xc210
Capability List support: on
66 MHz capable: off
User Definable Features (UDF) support: off
Fast back-to-back capable: off
Data parity error detected: off
DEVSEL timing: medium (0x1)
Slave signaled Target Abort: off
Master received Target Abort: off
Master received Master Abort: off
Asserted System Error (SERR): on
Parity error detected: on
Class Name: bridge (0x06)
Subclass Name: CardBus (0x07)
Interface: 0x00
Revision ID: 0x01
BIST: 0x00
Header Type: 0x02 (0x02)
Latency Timer: 0x40
Cache Line Size: 0x10
Type 2 (PCI-CardBus bridge) header:
0x10: 0xcffe0000 0x020000a0 0x40040403 0xfffff000
0x20: 0x00000000 0xfffff000 0x00000000 0xfffffffc
0x30: 0x00000000 0xfffffffc 0x00000000 0x04e3010a
0x40: 0x14121524 0x00000001
Base address register at 0x10 (CardBus socket/ExCA registers)
type: 32-bit nonprefetchable memory
base: 0xcffe0000, not sized
Capability list pointer: 0xa0
Secondary status register: 0x0200
66 MHz capable: off
User Definable Features (UDF) support: off
Fast back-to-back capable: off
Data parity error detected: off
DEVSEL timing: medium (0x1)
Signalled target abort: off
Received target abort: off
Received master abort: off
Received system error: off
Detected parity error: off
PCI bus number: 0x03
CardBus bus number: 0x04
Subordinate bus number: 0x04
CardBus latency timer: 0x40
CardBus memory region 0:
base register: 0xfffff000
limit register: 0x00000000
CardBus memory region 1:
base register: 0xfffff000
limit register: 0x00000000
CardBus I/O region 0:
base register: 0xfffffffc
limit register: 0x00000000
CardBus I/O region 1:
base register: 0xfffffffc
limit register: 0x00000000
Interrupt line: 0x0a
Interrupt pin: 0x01 (pin A)
Bridge control register: 0x04e3
Parity error response: on
SERR# enable: on
ISA enable: off
VGA enable: off
Master abort mode: on
Secondary (CardBus) bus reset: on
Functional interrupts routed by ExCA registers: on
Memory window 0 prefetchable: off
Memory window 1 prefetchable: off
Write posting enable: on
Subsystem vendor ID: 0x1524
Subsystem ID: 0x1412
Base address register at 0x44 (legacy-mode registers)
type: i/o
base: 0x00000000, not sized
Capability register at 0xa0
type: 0x01 (Power Management, rev. 1.0)
PCI Power Management Capabilities Register
Capabilities register: 0xfe01
Version: 1.0
PME# clock: off
Device specific initialization: off
3.3V auxiliary current: self-powered
D1 power management state support: on
D2 power management state support: on
PME# support: 0x1f
Control/status register: 0x0000
Power state: D0
PCI Express reserved: off
No soft reset: off
PME# assertion disabled
PME# status: off
Device-dependent header:
0x48: 0x00000000 0x00000000
0x50: 0x00000000 0x00000000 0x00000000 0x00000000
0x60: 0x00000000 0x00000000 0x00000000 0x00000000
0x70: 0x00000000 0x00000000 0x00000000 0x00000000
0x80: 0x0040d020 0x00000000 0x00000000 0x00801202
0x90: 0x604400c0 0x00000000 0x00000000 0x00000000
0xa0: 0xfe010001 0x00c00000 0x0000001e 0x0000001f
0xb0: 0x08000000 0x00000000 0x00000000 0x00000000
0xc0: 0x00001000 0x00800080 0x10000000 0x00000000
0xd0: 0x00000000 0x00000000 0x00000000 0x00000000
0xe0: 0x00000000 0x00000000 0x00000000 0x00000000
0xf0: 0x00000000 0x00000000 0x00000000 0x00000000
David> It looks to me like the PCI-CardBus bridge BAR is outside
David> of the address range forwarded by the PCI-PCI bridge.
David> cbb(4) may be reading/writing arbitrary addresses in RAM or
David> something.
I'm curious about your explanation.
Thanks in advance,
Markus.
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