Re: Workaround for AGP + Intel Q45

[Arnaud Lacombe <lacombar%gmail.com@localhost>]

Hi,

On Sun, Feb 8, 2009 at 5:05 AM, Michael Stapelberg
<michael+netbsd%stapelberg.de@localhost> wrote:
> Hi,
>
> first off: Please CC me in replies as I'm not on this list.
>
> I've got an Intel DQ45CB Mainboard and wanted to use the integrated graphics.
> After some debugging, I've found out that in src/sys/dev/pci/agp_i810.c in
> agp_i810_get_aperture(), there is no default value for aperture size.
>
> My BIOS has an option for how much RAM to use for the graphics chip. Choices
> are 128 MB and 256 MB. As in the current code, only 256 and 512 MB are an
> option, I'd say introducing 128 MB as (temporary) fallback would be a good
> idea, so that people can actually use their hardware until this is really
> fixed.
>
> If you want to do this by your own: Add the following to the
> switch()-statement in CHIP_G4X:
> default:
>        size = 128 * 1024 * 1024;
>
No, this is wrong. Default seems to be 256MB, with custom register
value for 128MB. I am missing a connection between Intel data sheets:
the "Intel(R) 4 Series Chipset Family"[0] says about the aperture
size:

9.1.11 GMADR—Graphics Memory Range Address
[...]
512MB Address Mask (512ADMSK): This Bit is either
part of the Memory Base Address (R/W) or part of the
depending on the value of MSAC[2:1].
See MSAC (Device 2, Function 0, offset 62h) for details.

However, there is no entry for offset 62h in this datasheet.

If I check the "Intel(R) 965 Express Chipset Family and Intel(R) G35
Express Chipset Graphics Controller PRM"[1], it says:

7.2.29 MSAC — Multi Size Aperture Control
       B/D/F/Type:                            0/2/0/PCI
       Address Offset:                        62h
       Default Value:                         02h
       Access:                                RO; R/W; R/W/L;
       Size:                                  8 bits
       This register determines the size of the graphics memory
aperture in function 0. By
       default the aperture size is 256 MB. Only the system BIOS will
write this register
       based on pre-boot address allocation efforts, but the graphics
may read this register
       to determine the correct aperture size. System BIOS needs to
save this value on boot
       so that it can reset it correctly during S3 resume.

This does not apply to the G45 (if I trust the title of the document).
However, this PRM has been released on Jan08 when the G45 chipset was
not available. I'm not sure Intel released a newer documentation
since. In any case, I think I screwed things up by setting
AGP_G4X_MSAC to 0x64, I think it should be 0x60, but I'm not sure
unless I find a datasheet explicitly saying this. I used 0x64 because
a of comment in the original FreeBSD code saying that G45 were like
G965. On G965, MSAC is at offset 0x66 (ie. 0x64 to have aligned PCI
access). But the G965 data sheet is not coherent as the default value
is 0x02 which is an illegal programming...

So definitively, I am missing something... :(

 - Arnaud

[0]: www.intel.com/Assets/PDF/datasheet/319970.pdf
[1]: http://www.x.org/docs/intel/VOL_2_graphics_core.pdf