Re: Question about caching

[Hauke Fath <hauke%Espresso.Rhein-Neckar.DE@localhost>]

At 17:37 Uhr -0700 25.8.2009, Jason Thorpe wrote:
>If a page is mapped into multiple pmaps (e.g. kernel pmap and a user
>pmap), and one of those mappings is cache-inhibited, do all of the
>mappings need to be cache-inhibited?

Looking through the 68040 manual PDF, ch. 3.1.3 (Transparent translation
registers) discusses the cache mode bits, and refers to ch. 4 (instruction
and data caches). It does not discuss multiple (overlapping) mappings
there.

Ch. 4.3.2  (cache inhibited accesses) discusses how the CM field determines
caching, but again does not talk about multiple mappings.

>My feeling is that the answer is "yes".

Certainly a safe bet, given Motorola's silence on the issue.

I can throw the CPU manual pdfs your way if it helps.

        hauke

--
"It's never straight up and down"     (DEVO)