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Re: Question about caching
- Subject: Re: Question about caching
- From: Ignatios Souvatzis <is%netbsd.org@localhost>
- Date: Thu, 27 Aug 2009 21:58:28 +0200
On Thu, Aug 27, 2009 at 07:43:16PM +0000, Michael van Elst wrote:
> agrier%poofygoof.com@localhost ("Aaron J. Grier") writes:
>
> >On Thu, Aug 27, 2009 at 11:03:55AM -0700, Jason Thorpe wrote:
> >> Ping? Does no one else remember either? :-)
>
> >wow, MMU _and_ cache! :)
>
> >which 68k variants we talking about here?
>
> Every single 68k that runs NetBSD.
>
> To answer the question, the chip should generate the bus cycles
> that you ask it for. If you use a mapping that inhibits caching
> then you get 1:1 bus cycles, if you use a mapping that allows
> caching you get cache fill and push cycles. Using two mappings
> to the same physical address but with different cache modes
> rarely makes no sense.
... but would work on 68040 at least, if you insist.
-is
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