The line that controls it in mesongxbb_clkc.c is this:
MESON_CLK_GATE(MESONGXBB_CLOCK_I2C, "i2c", "clk81", HHI_GCLK_MPEG0, 9),
MESONGXBB_CLOCK_I2C is 22, that is what matches against the value of the
'clocks' property in the device tree node.
The rest of it just specifies bit 9 of the register at 0x50 (HHI_GCLK_MPEG0)
to enable it.
Thank you! :)