Re: athn status - WN861N support?

[Sébastien Bocahu <lists%zecrazytux.net@localhost>]

> >   athn0 at pci0 dev 17 function 0
> >   athn0: cannot map register space
> 
> Can you please provide the output of "pcictl dump" for this device?

Here it is...

Thanks !

----


PCI configuration registers:
  Common header:
    0x00: 0x0028168c 0x82b00106 0x02800010 0x0000a808

    Vendor Name: Atheros Communications (0x168c)
    Device ID: 0x0028
    Command register: 0x0106
      I/O space accesses: off
      Memory space accesses: on
      Bus mastering: on
      Special cycles: off
      MWI transactions: off
      Palette snooping: off
      Parity error checking: off
      Address/data stepping: off
      System error (SERR): on
      Fast back-to-back transactions: off
      Interrupt disable: off
    Status register: 0x82b0
      Interrupt status: inactive
      Capability List support: on
      66 MHz capable: on
      User Definable Features (UDF) support: off
      Fast back-to-back capable: on
      Data parity error detected: off
      DEVSEL timing: medium (0x1)
      Slave signaled Target Abort: off
      Master received Target Abort: off
      Master received Master Abort: off
      Asserted System Error (SERR): off
      Parity error detected: on
    Class Name: network (0x02)
    Subclass Name: miscellaneous (0x80)
    Interface: 0x00
    Revision ID: 0x10
    BIST: 0x00
    Header Type: 0x00 (0x00)
    Latency Timer: 0xa8
    Cache Line Size: 0x08

  Type 0 ("normal" device) header:
    0x10: 0x00100000 0x00000000 0x00000000 0x00000000
    0x20: 0x00000000 0x00000000 0x00000000 0x2090168c
    0x30: 0x00000000 0x00000044 0x00000000 0x0000010e

    Base address register at 0x10
      type: 32-bit nonprefetchable memory
      base: 0x00100000, not sized
    Base address register at 0x14
      not implemented(?)
    Base address register at 0x18
      not implemented(?)
    Base address register at 0x1c
      not implemented(?)
    Base address register at 0x20
      not implemented(?)
    Base address register at 0x24
      not implemented(?)
    Cardbus CIS Pointer: 0x00000000
    Subsystem vendor ID: 0x168c
    Subsystem ID: 0x2090
    Expansion ROM Base Address: 0x00000000
    Capability list pointer: 0x44
    Reserved @ 0x38: 0x00000000
    Maximum Latency: 0x00
    Minimum Grant: 0x00
    Interrupt pin: 0x01 (pin A)
    Interrupt line: 0x0e

  Capability register at 0x44
    type: 0x00 (reserved)

  Device-dependent header:
    0x40: 0x00000080 0x48820000 0x00000000 0x00000000
    0x50: 0x00000000 0x00000000 0x00000000 0x00000000
    0x60: 0x00000000 0x00000000 0x00000000 0x00000000
    0x70: 0x00000000 0x00000000 0x00000000 0x00000000
    0x80: 0x00000000 0x00000000 0x00000000 0x00000000
    0x90: 0x00000000 0x00000000 0x00000000 0x00000000
    0xa0: 0x00000000 0x00000000 0x00000000 0x00000000
    0xb0: 0x00000000 0x00000000 0x00000000 0x00000000
    0xc0: 0x00000000 0x00000000 0x00000000 0x00000000
    0xd0: 0x00000000 0x00000000 0x00000000 0x00000000
    0xe0: 0x00000000 0x00000000 0x00000000 0x00000000
    0xf0: 0x00000000 0x00000000 0x00000000 0x00000000