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Re: tlp(4) DMA synchronization
On Aug 27, 2009, at 4:57 PM, David Young wrote:
We may be able to use cacheline-aligned descriptors in ring mode if
chip respects the Descriptor Skip Length (DSL) field of the Bus Mode
Register. According to the datasheet, the DSL field "Specifies the
number of longwords to skip between two unchained descriptors."
What do you think?
Sorry this is late...
Not all of the clones support DSL, and not all of the clones support
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