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Re: tlp(4) DMA synchronization

On Fri, Aug 28, 2009 at 08:21:38AM +0900, Izumi Tsutsui wrote:
> > I made a patch to complete/optimize DMA synchronization in tlp(4),
> > does it look correct?  URL:
> > 
> >
> >> +                  TULIP_CDRXSYNC(sc, i,
> >> +                      BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
>  :
> >> +          if (txstat & TDSTAT_OWN) {
> >> +                  TULIP_CDTXSYNC(sc, txs->txs_lastdesc, 1,
> >> +                      BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
> Only BUS_DMASYNC_PREREAD is enough because
> no write (host -> device) op will happen after
> these pollings.
> These ops are required on systems which don't handle BUS_DMA_COHERENT.

According to the documentation, we cannot count on BUS_DMA_COHERENT to
do anything, so the ops are always required. :-)

> But strictly speaking, on such system we'd have to use chained mode
> (not ring mode) with proper padded between each DMA descriptor,
> i.e. one descriptor per cacheline to avoid host vs DMA race.

You're right, of course.  I have seen these races occur on architectures
that we aim to support, such as ARM.

I think that in principle, the host can use ring mode if does not reuse
a descriptor until after the NIC has relinquished every other descriptor
in the same cacheline.

We may be able to use cacheline-aligned descriptors in ring mode if the
chip respects the Descriptor Skip Length (DSL) field of the Bus Mode
Register.  According to the datasheet, the DSL field "Specifies the
number of longwords to skip between two unchained descriptors."

What do you think?


David Young             OJC Technologies      Urbana, IL * (217) 278-3933

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