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Re: maintainers/users of de(4), lmc(4) ?
On Sun, Aug 30, 2009 at 05:01:48PM +0100, David Laight wrote:
> One possibility is to write each signal value multiple times - using
> the bus timings to control the bit-bang rate. For 33MHz PCI that is
> 60ns per extra write, but I can't remember the bit-band rate needed.
I used this technique, backwards, in the hifn driver, because the hifn
RNG hardware is missing a latch on one key register due to a hardware
design mistake. So you generate some extra bus traffic but don't lock
up the whole kernel spinning -- it seems like a fair trade to me.
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