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Re: maintainers/users of de(4), lmc(4) ?
On Wed, Aug 26, 2009 at 08:13:14PM +0900, Izumi Tsutsui wrote:
> mii_bitbang.c also uses delay(9) to generate clock plus,
> so I wonder how delay(9) is/was implemented on cats.
Hmmm... 'posted writes' (etc) mean the delay(9) is rather inappropriate
for generating the signal delays required for bit-banging.
Adding adequate loop delay also spins the kernel for significant periods
(especially if multiple registers are being accessed).
One possibility is to write each signal value multiple times - using
the bus timings to control the bit-bang rate. For 33MHz PCI that is
60ns per extra write, but I can't remember the bit-band rate needed.
For polling for link status change, it ought to be possible to do
one transition per timer tick! This might mean it takes 1 second to
detect media change ...
The big fubar with the MII interface, is that none of the standard
registers (0..7 of 15 IIRC) contain the actual operating mode!
(In particular FDX v HDX - where the MAC has to agree with the PHY.)
David Laight: david%l8s.co.uk@localhost
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