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Re: CVS commit: src/sys/arch/mips/mips

On Mon, Nov 08, 2010 at 03:49:09PM -0700, Warner Losh wrote:
 >>> I don't have a mips1-specific reference on hand, but my recollection
 >>> is that you need *three* nops when messing with cop0 registers for all
 >>> effects to flush through.
 >> locore_mips1.S doesn't agree with your recollection, e.g. mips1_TLBUpdate
 >> right above mips1_TLBRead.

What about it? It has some nops scattered in it, but they're neither
documented nor particularly systematic.

 > mips1 had a 2 stage pipeline, so at most you'd need 1 nop.  3 nops
 > is for the R4000's and similar.

I'm not sure about that. The only docs I still have do not describe
the 3-cycle wait for interrupt switching as r4000-specific, although
these docs do describe other pipeline hazards as r4000-specific. That
doesn't prove much for certain, but it's at least suggestive.

(I used to have the Hennessey & Patterson textbook that described the
original r2000 in gory detail, but I got rid of it because it was

Anyway, the exactly one nop that you do see in some mips1 contexts
(e.g. branch delays, and using values after fetching them) is the
offset between certain pipeline stages, not the total pipeline depth.

 > Then it got weird with multi-issue, threads, and sometimes silicon
 > bugs that required more before MIPS32r2 and MIPS64r2 codified a
 > single, special kind of nop that did the trick.

You still need more than one of those in some cases, to the best of my

David A. Holland

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