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Re: CVS commit: src/sys/arch/mips/mips
On 11/08/2010 15:19, Antti Kantee wrote:
mips1 had a 2 stage pipeline, so at most you'd need 1 nop. 3 nops is
for the R4000's and similar. Then it got weird with multi-issue,
threads, and sometimes silicon bugs that required more before MIPS32r2
and MIPS64r2 codified a single, special kind of nop that did the trick.
On Mon Nov 08 2010 at 21:40:49 +0000, David Holland wrote:
On Mon, Nov 08, 2010 at 06:09:39PM +0000, Antti Kantee wrote:
> Modified Files:
> src/sys/arch/mips/mips: locore_mips1.S
> Log Message:
> In TLBRead, restore PID before doing the saves so that the caller's
> TLB entries are used instead of the PID given as the argument.
> from Alessandro Forin
This doesn't make any sense.
As far as I can tell, the real problem is that the code is not
attending to pipeline hazards properly; moving things around until it
experimentally seems to work is just going to create other odd
behavior sometime down the line under different timing circumstances.
I don't have a mips1-specific reference on hand, but my recollection
is that you need *three* nops when messing with cop0 registers for all
effects to flush through.
locore_mips1.S doesn't agree with your recollection, e.g. mips1_TLBUpdate
right above mips1_TLBRead.
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