Re: Question about caching

[Michael van Elst <mlelstv%serpens.de@localhost>]

On Wed, Sep 09, 2009 at 02:22:21PM -0700, Jason Thorpe wrote:

> I'm mostly interested in coherency of regular memory with cached vs  
> uncached mappings.

The 68040 manual (section 4.5) makes the following statement:

<quote>
Because each cache line reflects page state information, a page should
be flushed from the cache before any of the page attributes are changed.
The presence of a valid or dirty cache line implicitely indicates that
accesses to the page containing the line are cachable. The presence of
a dirty cache line implies that the page is not write protected and that
writes to the page are in copyback mode.
</quote>

My interpretation is that changed page attributes are equivalent to
two mappings with different attributes and that coherency is maintained.

On the other hand, there probably was a reason for using uncached memory
(i.e. some DMA device without snooping capability) and the chip might
ignore this if there is still valid data in the cache.  The programmer
should avoid this situation.

N.B. the instruction cache is something different.

Greetings,
-- 
                                Michael van Elst
Internet: mlelstv%serpens.de@localhost
                                "A potential Snark may lurk in every tree."