agrier%poofygoof.com@localhost ("Aaron J. Grier") writes:
On Thu, Aug 27, 2009 at 11:03:55AM -0700, Jason Thorpe wrote:
Ping? Does no one else remember either? :-)
wow, MMU _and_ cache! :)
which 68k variants we talking about here?
Every single 68k that runs NetBSD.
To answer the question, the chip should generate the bus cycles
that you ask it for. If you use a mapping that inhibits caching
then you get 1:1 bus cycles, if you use a mapping that allows
caching you get cache fill and push cycles. Using two mappings
to the same physical address but with different cache modes
rarely makes no sense.