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Re: Generic startup code maps memory non-cacheable non-shareable

Doh, there was a mistake in my code to enable the SCU so it was actually
not enabled. So now, with the addition of all the missing bootstrapping
code, "it works". I would still like your answers to help me understand
why (except for the dmesg which I don't need anymore).


Aymeric Vincent <aymericvincent%free.fr@localhost> writes:

> For it to work, arm_cpu_hatched and arm_cpu_mbox need to be mapped with
> the cacheable and shareable bits on. When is this supposed to be done?
> (I guess this incurs switching level 1 page tables.) I don't see in the
> code why it would be done in time on the iMX6 and not on the Cyclone V
> given arm_cpu_hatched is accessed very early during bootup of the
> secondary processors.
> Secondly, could you please share the VERBOSE_INIT_ARM dmesg of the
> working iMX6 port so I can see the order in which things happen?
> And finally, could you please say why we switched to mapping the kernel
> not cacheable and not shareable during startup?

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