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Re: Generic startup code maps memory non-cacheable non-shareable

Nick Hudson <nick.hudson%gmx.co.uk@localhost> writes:

> Because ap_mpstart is called on BP where L2 cache initialisation is
> done before the APs are started and the arm_cpu_hatched dance is
> needed

For it to work, arm_cpu_hatched and arm_cpu_mbox need to be mapped with
the cacheable and shareable bits on. When is this supposed to be done?
(I guess this incurs switching level 1 page tables.) I don't see in the
code why it would be done in time on the iMX6 and not on the Cyclone V
given arm_cpu_hatched is accessed very early during bootup of the
secondary processors.

Secondly, could you please share the VERBOSE_INIT_ARM dmesg of the
working iMX6 port so I can see the order in which things happen?

And finally, could you please say why we switched to mapping the kernel
not cacheable and not shareable during startup?


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