Port-arm archive

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index][Old Index]

Generic startup code maps memory non-cacheable non-shareable


The new generic startup code (at least for armv7 which I looked at) maps
all the kernel memory as non cacheable and non shareable.

It breaks secondary CPUs bootstrapping at least on Cortex A9's because
they rely on the L1 cache coherency provided by the snoop control unit
to exchange status through arm_cpu_hatched and arm_cpu_mbox. The SCU
works only for memory marked cacheable and shareable.

I can bootstrap the secondary CPU by adding the relevant cache
flushes/invalidations where due, but then the PIC fails in
intr_ipi_send() and I expect it's another instance of the same problem.

It seems wrong to me to avoid cacheable memory for the whole startup,
and I feel we should revert to using cacheable memory as much as
possible. What are the benefits of these no-cache mappings?

And, is noone else bitten by this?


Home | Main Index | Thread Index | Old Index