On 02/11/2018 13:33, Aymeric Vincent wrote:
Hi, The new generic startup code (at least for armv7 which I looked at) maps all the kernel memory as non cacheable and non shareable. It breaks secondary CPUs bootstrapping at least on Cortex A9's because they rely on the L1 cache coherency provided by the snoop control unit to exchange status through arm_cpu_hatched and arm_cpu_mbox. The SCU works only for memory marked cacheable and shareable.
https://nxr.netbsd.org/xref/src/sys/arch/evbarm/nitrogen6/nitrogen6_machdep.c#202 Is an example of a working ap_mpstart for Cortex A9 system. Nick