Port-arm archive

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index][Old Index]

Re: Generic startup code maps memory non-cacheable non-shareable

On 02/11/2018 13:33, Aymeric Vincent wrote:

The new generic startup code (at least for armv7 which I looked at) maps
all the kernel memory as non cacheable and non shareable.

It breaks secondary CPUs bootstrapping at least on Cortex A9's because
they rely on the L1 cache coherency provided by the snoop control unit
to exchange status through arm_cpu_hatched and arm_cpu_mbox. The SCU
works only for memory marked cacheable and shareable.


Is an example of a working ap_mpstart for Cortex A9 system.


Home | Main Index | Thread Index | Old Index