Re: MSI/MSI-X implementation and interrupt handling on i386/amd64

[Kengo NAKAHARA <k-nakahara%iij.ad.jp@localhost>]

Hi,

On 2018/12/11 6:49, Jaromír Doleček wrote:
> Le jeu. 6 déc. 2018 à 16:05, Cherry G.Mathew <cherry%zyx.in@localhost> a écrit :
>> The right thing to do is to stop using a bit mask entirely, and using
>> a bit more scalable Data structure for this. This isn't trivial though -
>> the assembler stuff will be harder to maintain correctness than a
>> straightup buslocked bitscan/compare etc.
> 
> What about just bumping this to 64 on amd64, where we have the 64-bit
> atomic ops? While keeping i386 still on 32.
> 
> We seem to have already i386 and amd64 variants of the interrupt
> assembler, so maybe not so bad that they would diverge further.
> 
> It would be nice to do something to bump the limit. If we have general
> consensus is that this is worth doing, I can try to write something
> and see how ugly/difficult it would become with 64bit bitmasks. I
> don't feel like delving into rewriting this to use completely
> different structure ...

I agree it.

I mention some old Athlon 64 series (before socket AM2) do not support 
cmpxchg16b instruction. That would affect rewriting spllower to support
64 bit interrupt bitmask.


Thanks,

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Kengo NAKAHARA <k-nakahara%iij.ad.jp@localhost>