Hi is,
got it to work against 5.99.44 for static ip, not yet dhcp
steps:
downloaded 5.99.44 source
compile and install tools/userland
applied alcdiff patch
ran make -f dev/pci/Makefile.pcidevs
adjust conf and compile MONOLITHIC kernel
kernel configuration changes:
added
#alc driver for Atheros L1E Gigabit Ethernet
alc* at pci? dev ? function ? # Atheros L1 Gigabit Ethernet (EXP)
atphy* at mii? phy ? # Attansic/Atheros PHYs
compile MONOLITHIC kernel
and commented out hdaudio becuase it causes my laptop to crashes
worked after running commands in test_alc.sh
ifconfig alc0 ${inet} netmask 0xffffff00
route add default ${gateway}
echo 'nameserver '${dns} >> /etc/resolv.conf
host netbsd.org
which worked.
the device is very sensative to order though, if I unplugged the cord
and ran the test_alc.sh it would say "alc0: watchdog timeout
(missing-link)"
which is to be expected
but if I plugged in back it in keep saying
"alc0: watchdog timeout"
so it seams like the cold has to be live when the ifconfig comand is
made the first time or it gets stuck in watchdog timout land.
~best
+
| fire crow
| computer programmer
!_____________________
http://firecrow.com, fire%firecrow.com@localhost, 917.306.9451, New York
City, USA
---------- Forwarded message ----------
From: Ignatios Souvatzis <is%netbsd.org@localhost>
Date: Fri, Jan 21, 2011 at 5:06 AM
Subject: Re: AR8131/2 driver
To: fire crow <fire%firecrow.com@localhost>
On Wed, Jan 19, 2011 at 11:07:12AM -0500, fire crow wrote:
> yeah I can totally alpha test for this, or at least I'm up for trying,
> send me stuff to get started.
>
> send me both I guess, a diff against current and the kernel, and I'll
> try both, trying the kernel is easy
> cause I can just pop it in.
>
> excellent about the BE filter,
it was actually already in, when I first created the stuff according
to your instructions. Anyway here's the diff to -current current.
After applying the patch, run "make -f Makefile.pcidevs USETOOLS=no"
in the directory "sys/dev/pci/".
Regards,
-is
--
seal your e-mail: http://www.gnupg.org/
--
Index: sys/dev/pci/files.pci
===================================================================
RCS file: /cvsroot/src/sys/dev/pci/files.pci,v
retrieving revision 1.335
diff -u -r1.335 files.pci
--- sys/dev/pci/files.pci 11 Dec 2010 18:18:09 -0000 1.335
+++ sys/dev/pci/files.pci 21 Jan 2011 09:37:58 -0000
@@ -970,6 +970,11 @@
attach age at pci
file dev/pci/if_age.c age
+# Attansic/Atheros L1C/L2C Gigabit Ethernet
+device alc: ether, ifnet, arp, mii, mii_phy
+attach alc at pci
+file dev/pci/if_alc.c alc
+
# Attanisc/Atheros L1E Gigabit Ethernet
device ale: ether, ifnet, arp, mii, mii_phy
attach ale at pci
Index: sys/dev/pci/pcidevs
===================================================================
RCS file: /cvsroot/src/sys/dev/pci/pcidevs,v
retrieving revision 1.1055
diff -u -r1.1055 pcidevs
--- sys/dev/pci/pcidevs 11 Jan 2011 00:13:03 -0000 1.1055
+++ sys/dev/pci/pcidevs 21 Jan 2011 09:37:59 -0000
@@ -1099,7 +1099,8 @@
/* Attansic Technology Corp. */
product ATTANSIC ETHERNET_L1E 0x1026 L1E Gigabit Ethernet Adapter
product ATTANSIC ETHERNET_GIGA 0x1048 L1 Gigabit Ethernet Adapter
-product ATTANSIC AR8131 0x1063 Atheros AR8131 Gigabit Ethernet
Adapter
+product ATTANSIC ETHERNET_L2C 0x1062 L2C Gigabit Ethernet Adapter
+product ATTANSIC ETHERNET_L1C 0x1063 L1C Gigabit Ethernet Adapter
product ATTANSIC ETHERNET_100 0x2048 L2 100 Mbit Ethernet Adapter
/* ATI products */
--- /dev/null 2011-01-21 10:30:24.000000000 +0100
+++ sys/dev/pci/if_alc.c 2011-01-16 12:59:36.000000000 +0100
@@ -0,0 +1,2371 @@
+/* $OpenBSD: if_alc.c,v 1.1 2009/08/08 09:31:13 kevlo Exp $ */
+/*-
+ * Copyright (c) 2009, Pyun YongHyeon <yongari%FreeBSD.org@localhost>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice unmodified, this list of conditions, and the following
+ * disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/* Driver for Atheros AR8131/AR8132 PCIe Ethernet. */
+
+#include "vlan.h"
+
+#include <sys/param.h>
+#include <sys/proc.h>
+#include <sys/endian.h>
+#include <sys/systm.h>
+#include <sys/types.h>
+#include <sys/sockio.h>
+#include <sys/mbuf.h>
+#include <sys/queue.h>
+#include <sys/kernel.h>
+#include <sys/device.h>
+#include <sys/callout.h>
+#include <sys/socket.h>
+
+#include <sys/bus.h>
+
+#include <net/if.h>
+#include <net/if_dl.h>
+#include <net/if_llc.h>
+#include <net/if_media.h>
+#include <net/if_ether.h>
+
+#ifdef INET
+#include <netinet/in.h>
+#include <netinet/in_systm.h>
+#include <netinet/in_var.h>
+#include <netinet/ip.h>
+#endif
+
+#include <net/if_types.h>
+#include <net/if_vlanvar.h>
+
+#include <net/bpf.h>
+
+#include <sys/rnd.h>
+
+#include <dev/mii/mii.h>
+#include <dev/mii/miivar.h>
+
+#include <dev/pci/pcireg.h>
+#include <dev/pci/pcivar.h>
+#include <dev/pci/pcidevs.h>
+
+#include <dev/pci/if_alcreg.h>
+
+static int alc_match(device_t, cfdata_t, void *);
+static void alc_attach(device_t, device_t, void *);
+static int alc_detach(device_t, int);
+
+static int alc_init(struct ifnet *);
+static void alc_start(struct ifnet *);
+static int alc_ioctl(struct ifnet *, u_long, void *);
+static void alc_watchdog(struct ifnet *);
+static int alc_mediachange(struct ifnet *);
+static void alc_mediastatus(struct ifnet *, struct ifmediareq *);
+
+static void alc_aspm(struct alc_softc *);
+static void alc_disable_l0s_l1(struct alc_softc *);
+static int alc_dma_alloc(struct alc_softc *);
+static void alc_dma_free(struct alc_softc *);
+static int alc_encap(struct alc_softc *, struct mbuf **);
+static void alc_get_macaddr(struct alc_softc *);
+static void alc_init_cmb(struct alc_softc *);
+static void alc_init_rr_ring(struct alc_softc *);
+static int alc_init_rx_ring(struct alc_softc *);
+static void alc_init_smb(struct alc_softc *);
+static void alc_init_tx_ring(struct alc_softc *);
+static int alc_intr(void *);
+static void alc_mac_config(struct alc_softc *);
+static int alc_miibus_readreg(device_t, int, int);
+static void alc_miibus_statchg(device_t);
+static void alc_miibus_writereg(device_t, int, int, int);
+static int alc_newbuf(struct alc_softc *, struct alc_rxdesc *, int);
+static void alc_phy_down(struct alc_softc *);
+static void alc_phy_reset(struct alc_softc *);
+static void alc_reset(struct alc_softc *);
+static void alc_rxeof(struct alc_softc *, struct rx_rdesc *);
+static int alc_rxintr(struct alc_softc *);
+static void alc_iff(struct alc_softc *);
+static void alc_rxvlan(struct alc_softc *);
+static void alc_start_queue(struct alc_softc *);
+static void alc_stats_clear(struct alc_softc *);
+static void alc_stats_update(struct alc_softc *);
+static void alc_stop(struct ifnet *, int);
+static void alc_stop_mac(struct alc_softc *);
+static void alc_stop_queue(struct alc_softc *);
+static void alc_tick(void *);
+static void alc_txeof(struct alc_softc *);
+
+uint32_t alc_dma_burst[] = { 128, 256, 512, 1024, 2048, 4096, 0 };
+
+CFATTACH_DECL_NEW(alc, sizeof(struct alc_softc),
+ alc_match, alc_attach, alc_detach, NULL);
+
+int alcdebug = 0;
+#define DPRINTF(x) do { if (alcdebug) printf x; } while (0)
+
+#define ETHER_ALIGN 2
+#define ALC_CSUM_FEATURES (M_CSUM_TCPv4 | M_CSUM_UDPv4)
+
+static int
+alc_miibus_readreg(device_t dev, int phy, int reg)
+{
+ struct alc_softc *sc = device_private(dev);
+ uint32_t v;
+ int i;
+
+ if (phy != sc->alc_phyaddr)
+ return (0);
+
+ CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ |
+ MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));
+ for (i = ALC_PHY_TIMEOUT; i > 0; i--) {
+ DELAY(5);
+ v = CSR_READ_4(sc, ALC_MDIO);
+ if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0)
+ break;
+ }
+
+ if (i == 0) {
+ printf("%s: phy read timeout: phy %d, reg %d\n",
+ device_xname(sc->sc_dev), phy, reg);
+ return (0);
+ }
+
+ return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT);
+}
+
+static void
+alc_miibus_writereg(device_t dev, int phy, int reg, int val)
+{
+ struct alc_softc *sc = device_private(dev);
+ uint32_t v;
+ int i;
+
+ if (phy != sc->alc_phyaddr)
+ return;
+
+ CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE |
+ (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT |
+ MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));
+ for (i = ALC_PHY_TIMEOUT; i > 0; i--) {
+ DELAY(5);
+ v = CSR_READ_4(sc, ALC_MDIO);
+ if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0)
+ break;
+ }
+
+ if (i == 0)
+ printf("%s: phy write timeout: phy %d, reg %d\n",
+ device_xname(sc->sc_dev), phy, reg);
+}
+
+static void
+alc_miibus_statchg(device_t dev)
+{
+ struct alc_softc *sc = device_private(dev);
+ struct ifnet *ifp = &sc->sc_ec.ec_if;
+ struct mii_data *mii;
+ uint32_t reg;
+
+ if ((ifp->if_flags & IFF_RUNNING) == 0)
+ return;
+
+ mii = &sc->sc_miibus;
+
+ sc->alc_flags &= ~ALC_FLAG_LINK;
+ if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
+ (IFM_ACTIVE | IFM_AVALID)) {
+ switch (IFM_SUBTYPE(mii->mii_media_active)) {
+ case IFM_10_T:
+ case IFM_100_TX:
+ sc->alc_flags |= ALC_FLAG_LINK;
+ break;
+ case IFM_1000_T:
+ if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0)
+ sc->alc_flags |= ALC_FLAG_LINK;
+ break;
+ default:
+ break;
+ }
+ }
+ alc_stop_queue(sc);
+ /* Stop Rx/Tx MACs. */
+ alc_stop_mac(sc);
+
+ /* Program MACs with resolved speed/duplex/flow-control. */
+ if ((sc->alc_flags & ALC_FLAG_LINK) != 0) {
+ alc_start_queue(sc);
+ alc_mac_config(sc);
+ /* Re-enable Tx/Rx MACs. */
+ reg = CSR_READ_4(sc, ALC_MAC_CFG);
+ reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB;
+ CSR_WRITE_4(sc, ALC_MAC_CFG, reg);
+ }
+ alc_aspm(sc);
+}
+
+static void
+alc_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
+{
+ struct alc_softc *sc = ifp->if_softc;
+ struct mii_data *mii = &sc->sc_miibus;
+
+ mii_pollstat(mii);
+ ifmr->ifm_status = mii->mii_media_status;
+ ifmr->ifm_active = mii->mii_media_active;
+}
+
+static int
+alc_mediachange(struct ifnet *ifp)
+{
+ struct alc_softc *sc = ifp->if_softc;
+ struct mii_data *mii = &sc->sc_miibus;
+ int error;
+
+ if (mii->mii_instance != 0) {
+ struct mii_softc *miisc;
+
+ LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
+ mii_phy_reset(miisc);
+ }
+ error = mii_mediachg(mii);
+
+ return (error);
+}
+
+static int
+alc_match(device_t dev, cfdata_t match, void *aux)
+{
+ struct pci_attach_args *pa = aux;
+
+ return (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ATTANSIC &&
+ (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ATTANSIC_ETHERNET_L1C ||
+ PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ATTANSIC_ETHERNET_L2C));
+}
+
+static void
+alc_get_macaddr(struct alc_softc *sc)
+{
+ uint32_t ea[2], opt;
+ int i;
+
+ opt = CSR_READ_4(sc, ALC_OPT_CFG);
+ if ((CSR_READ_4(sc, ALC_TWSI_DEBUG) & TWSI_DEBUG_DEV_EXIST) != 0) {
+ /*
+ * EEPROM found, let TWSI reload EEPROM configuration.
+ * This will set ethernet address of controller.
+ */
+ if ((opt & OPT_CFG_CLK_ENB) == 0) {
+ opt |= OPT_CFG_CLK_ENB;
+ CSR_WRITE_4(sc, ALC_OPT_CFG, opt);
+ CSR_READ_4(sc, ALC_OPT_CFG);
+ DELAY(1000);
+ }
+ CSR_WRITE_4(sc, ALC_TWSI_CFG, CSR_READ_4(sc, ALC_TWSI_CFG) |
+ TWSI_CFG_SW_LD_START);
+ for (i = 100; i > 0; i--) {
+ DELAY(1000);
+ if ((CSR_READ_4(sc, ALC_TWSI_CFG) &
+ TWSI_CFG_SW_LD_START) == 0)
+ break;
+ }
+ if (i == 0)
+ printf("%s: reloading EEPROM timeout!\n",
+ device_xname(sc->sc_dev));
+ } else {
+ if (alcdebug)
+ printf("%s: EEPROM not found!\n",
device_xname(sc->sc_dev));
+ }
+ if ((opt & OPT_CFG_CLK_ENB) != 0) {
+ opt &= ~OPT_CFG_CLK_ENB;
+ CSR_WRITE_4(sc, ALC_OPT_CFG, opt);
+ CSR_READ_4(sc, ALC_OPT_CFG);
+ DELAY(1000);
+ }
+
+ ea[0] = CSR_READ_4(sc, ALC_PAR0);
+ ea[1] = CSR_READ_4(sc, ALC_PAR1);
+ sc->alc_eaddr[0] = (ea[1] >> 8) & 0xFF;
+ sc->alc_eaddr[1] = (ea[1] >> 0) & 0xFF;
+ sc->alc_eaddr[2] = (ea[0] >> 24) & 0xFF;
+ sc->alc_eaddr[3] = (ea[0] >> 16) & 0xFF;
+ sc->alc_eaddr[4] = (ea[0] >> 8) & 0xFF;
+ sc->alc_eaddr[5] = (ea[0] >> 0) & 0xFF;
+}
+
+static void
+alc_disable_l0s_l1(struct alc_softc *sc)
+{
+ uint32_t pmcfg;
+
+ /* Another magic from vendor. */
+ pmcfg = CSR_READ_4(sc, ALC_PM_CFG);
+ pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_CLK_SWH_L1 |
+ PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | PM_CFG_MAC_ASPM_CHK |
+ PM_CFG_SERDES_PD_EX_L1);
+ pmcfg |= PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB |
+ PM_CFG_SERDES_L1_ENB;
+ CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg);
+}
+
+static void
+alc_phy_reset(struct alc_softc *sc)
+{
+ uint16_t data;
+
+ /* Reset magic from Linux. */
+ CSR_WRITE_2(sc, ALC_GPHY_CFG,
+ GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | GPHY_CFG_SEL_ANA_RESET);
+ CSR_READ_2(sc, ALC_GPHY_CFG);
+ DELAY(10 * 1000);
+
+ CSR_WRITE_2(sc, ALC_GPHY_CFG,
+ GPHY_CFG_EXT_RESET | GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE |
+ GPHY_CFG_SEL_ANA_RESET);
+ CSR_READ_2(sc, ALC_GPHY_CFG);
+ DELAY(10 * 1000);
+
+ /* Load DSP codes, vendor magic. */
+ data = ANA_LOOP_SEL_10BT | ANA_EN_MASK_TB | ANA_EN_10BT_IDLE |
+ ((1 << ANA_INTERVAL_SEL_TIMER_SHIFT) & ANA_INTERVAL_SEL_TIMER_MASK);
+ alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr,
+ ALC_MII_DBG_ADDR, MII_ANA_CFG18);
+ alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr,
+ ALC_MII_DBG_DATA, data);
+
+ data = ((2 << ANA_SERDES_CDR_BW_SHIFT) & ANA_SERDES_CDR_BW_MASK) |
+ ANA_SERDES_EN_DEEM | ANA_SERDES_SEL_HSP | ANA_SERDES_EN_PLL |
+ ANA_SERDES_EN_LCKDT;
+ alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr,
+ ALC_MII_DBG_ADDR, MII_ANA_CFG5);
+ alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr,
+ ALC_MII_DBG_DATA, data);
+
+ data = ((44 << ANA_LONG_CABLE_TH_100_SHIFT) &
+ ANA_LONG_CABLE_TH_100_MASK) |
+ ((33 << ANA_SHORT_CABLE_TH_100_SHIFT) &
+ ANA_SHORT_CABLE_TH_100_SHIFT) |
+ ANA_BP_BAD_LINK_ACCUM | ANA_BP_SMALL_BW;
+ alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr,
+ ALC_MII_DBG_ADDR, MII_ANA_CFG54);
+ alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr,
+ ALC_MII_DBG_DATA, data);
+
+ data = ((11 << ANA_IECHO_ADJ_3_SHIFT) & ANA_IECHO_ADJ_3_MASK) |
+ ((11 << ANA_IECHO_ADJ_2_SHIFT) & ANA_IECHO_ADJ_2_MASK) |
+ ((8 << ANA_IECHO_ADJ_1_SHIFT) & ANA_IECHO_ADJ_1_MASK) |
+ ((8 << ANA_IECHO_ADJ_0_SHIFT) & ANA_IECHO_ADJ_0_MASK);
+ alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr,
+ ALC_MII_DBG_ADDR, MII_ANA_CFG4);
+ alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr,
+ ALC_MII_DBG_DATA, data);
+
+ data = ((7 & ANA_MANUL_SWICH_ON_SHIFT) & ANA_MANUL_SWICH_ON_MASK) |
+ ANA_RESTART_CAL | ANA_MAN_ENABLE | ANA_SEL_HSP | ANA_EN_HB |
+ ANA_OEN_125M;
+ alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr,
+ ALC_MII_DBG_ADDR, MII_ANA_CFG0);
+ alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr,
+ ALC_MII_DBG_DATA, data);
+ DELAY(1000);
+}
+
+static void
+alc_phy_down(struct alc_softc *sc)
+{
+
+ /* Force PHY down. */
+ CSR_WRITE_2(sc, ALC_GPHY_CFG,
+ GPHY_CFG_EXT_RESET | GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE |
+ GPHY_CFG_SEL_ANA_RESET | GPHY_CFG_PHY_IDDQ | GPHY_CFG_PWDOWN_HW);
+ DELAY(1000);
+}
+
+static void
+alc_aspm(struct alc_softc *sc)
+{
+ uint32_t pmcfg;
+
+ pmcfg = CSR_READ_4(sc, ALC_PM_CFG);
+ pmcfg &= ~PM_CFG_SERDES_PD_EX_L1;
+ pmcfg |= PM_CFG_SERDES_BUDS_RX_L1_ENB;
+ pmcfg |= PM_CFG_SERDES_L1_ENB;
+ pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_MASK;
+ pmcfg |= PM_CFG_MAC_ASPM_CHK;
+ if ((sc->alc_flags & ALC_FLAG_LINK) != 0) {
+ pmcfg |= PM_CFG_SERDES_PLL_L1_ENB;
+ pmcfg &= ~PM_CFG_CLK_SWH_L1;
+ pmcfg &= ~PM_CFG_ASPM_L1_ENB;
+ pmcfg &= ~PM_CFG_ASPM_L0S_ENB;
+ } else {
+ pmcfg &= ~PM_CFG_SERDES_PLL_L1_ENB;
+ pmcfg |= PM_CFG_CLK_SWH_L1;
+ pmcfg &= ~PM_CFG_ASPM_L1_ENB;
+ pmcfg &= ~PM_CFG_ASPM_L0S_ENB;
+ }
+ CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg);
+}
+
+static void
+alc_attach(device_t parent, device_t self, void *aux)
+{
+
+ struct alc_softc *sc = device_private(self);
+ struct pci_attach_args *pa = aux;
+ pci_chipset_tag_t pc = pa->pa_pc;
+ pci_intr_handle_t ih;
+ const char *intrstr;
+ struct ifnet *ifp;
+ pcireg_t memtype;
+ const char *aspm_state[] = { "L0s/L1", "L0s", "L1", "L0s/l1" };
+ uint16_t burst;
+ int base, mii_flags, state, error = 0;
+ uint32_t cap, ctl, val;
+
+ aprint_naive("\n");
+ aprint_normal(": Attansic/Atheros L1E Ethernet\n");
+
+ sc->sc_dev = self;
+ sc->sc_dmat = pa->pa_dmat;
+ sc->sc_pct = pa->pa_pc;
+ sc->sc_pcitag = pa->pa_tag;
+
+ /*
+ * Allocate IO memory
+ */
+ memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, ALC_PCIR_BAR);
+ switch (memtype) {
+ case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT:
+ case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT_1M:
+ case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT:
+ break;
+ default:
+ aprint_error_dev(self, "invalid base address register\n");
+ break;
+ }
+
+ if (pci_mapreg_map(pa, ALC_PCIR_BAR, memtype, 0, &sc->sc_mem_bt,
+ &sc->sc_mem_bh, NULL, &sc->sc_mem_size)) {
+ aprint_error_dev(self, "could not map mem space\n");
+ return;
+ }
+
+ if (pci_intr_map(pa, &ih) != 0) {
+ printf(": can't map interrupt\n");
+ goto fail;
+ }
+
+ /*
+ * Allocate IRQ
+ */
+ intrstr = pci_intr_string(sc->sc_pct, ih);
+ sc->sc_irq_handle = pci_intr_establish(pc, ih, IPL_NET, alc_intr, sc);
+ if (sc->sc_irq_handle == NULL) {
+ printf(": could not establish interrupt");
+ if (intrstr != NULL)
+ printf(" at %s", intrstr);
+ printf("\n");
+ goto fail;
+ }
+ aprint_normal_dev(self, "%s\n", intrstr);
+
+ /* Set PHY address. */
+ sc->alc_phyaddr = ALC_PHY_ADDR;
+
+ /* Initialize DMA parameters. */
+ sc->alc_dma_rd_burst = 0;
+ sc->alc_dma_wr_burst = 0;
+ sc->alc_rcb = DMA_CFG_RCB_64;
+ if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PCIEXPRESS,
+ &base, NULL)) {
+ sc->alc_flags |= ALC_FLAG_PCIE;
+ burst = pci_conf_read(sc->sc_pct, sc->sc_pcitag,
+ base + PCI_PCIE_DCSR) >> 16;
+ sc->alc_dma_rd_burst = (burst & 0x7000) >> 12;
+ sc->alc_dma_wr_burst = (burst & 0x00e0) >> 5;
+ if (alcdebug) {
+ printf("%s: Read request size : %u bytes.\n",
+ device_xname(sc->sc_dev),
+ alc_dma_burst[sc->alc_dma_rd_burst]);
+ printf("%s: TLP payload size : %u bytes.\n",
+ device_xname(sc->sc_dev),
+ alc_dma_burst[sc->alc_dma_wr_burst]);
+ }
+ /* Clear data link and flow-control protocol error. */
+ val = CSR_READ_4(sc, ALC_PEX_UNC_ERR_SEV);
+ val &= ~(PEX_UNC_ERR_SEV_DLP | PEX_UNC_ERR_SEV_FCP);
+ CSR_WRITE_4(sc, ALC_PEX_UNC_ERR_SEV, val);
+ /* Disable ASPM L0S and L1. */
+ cap = pci_conf_read(sc->sc_pct, sc->sc_pcitag,
+ base + PCI_PCIE_LCAP) >> 16;
+ if ((cap & 0x00000c00) != 0) {
+ ctl = pci_conf_read(sc->sc_pct, sc->sc_pcitag,
+ base + PCI_PCIE_LCSR) >> 16;
+ if ((ctl & 0x08) != 0)
+ sc->alc_rcb = DMA_CFG_RCB_128;
+ if (alcdebug)
+ printf("%s: RCB %u bytes\n",
+ device_xname(sc->sc_dev),
+ sc->alc_rcb == DMA_CFG_RCB_64 ? 64 : 128);
+ state = ctl & 0x03;
+ if (alcdebug)
+ printf("%s: ASPM %s %s\n",
+ device_xname(sc->sc_dev),
+ aspm_state[state],
+ state == 0 ? "disabled" : "enabled");
+ if (state != 0)
+ alc_disable_l0s_l1(sc);
+ }
+ }
+
+ /* Reset PHY. */
+ alc_phy_reset(sc);
+
+ /* Reset the ethernet controller. */
+ alc_reset(sc);
+
+ /*
+ * One odd thing is AR8132 uses the same PHY hardware(F1
+ * gigabit PHY) of AR8131. So atphy(4) of AR8132 reports
+ * the PHY supports 1000Mbps but that's not true. The PHY
+ * used in AR8132 can't establish gigabit link even if it
+ * shows the same PHY model/revision number of AR8131.
+ */
+ if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ATTANSIC_ETHERNET_L2C)
+ sc->alc_flags |= ALC_FLAG_FASTETHER | ALC_FLAG_JUMBO;
+ else
+ sc->alc_flags |= ALC_FLAG_JUMBO | ALC_FLAG_ASPM_MON;
+ /*
+ * It seems that AR8131/AR8132 has silicon bug for SMB. In
+ * addition, Atheros said that enabling SMB wouldn't improve
+ * performance. However I think it's bad to access lots of
+ * registers to extract MAC statistics.
+ */
+ sc->alc_flags |= ALC_FLAG_SMB_BUG;
+ /*
+ * Don't use Tx CMB. It is known to have silicon bug.
+ */
+ sc->alc_flags |= ALC_FLAG_CMB_BUG;
+ sc->alc_rev = PCI_REVISION(pa->pa_class);
+ sc->alc_chip_rev = CSR_READ_4(sc, ALC_MASTER_CFG) >>
+ MASTER_CHIP_REV_SHIFT;
+ if (alcdebug) {
+ printf("%s: PCI device revision : 0x%04x\n",
+ device_xname(sc->sc_dev), sc->alc_rev);
+ printf("%s: Chip id/revision : 0x%04x\n",
+ device_xname(sc->sc_dev), sc->alc_chip_rev);
+ printf("%s: %u Tx FIFO, %u Rx FIFO\n", device_xname(sc->sc_dev),
+ CSR_READ_4(sc, ALC_SRAM_TX_FIFO_LEN) * 8,
+ CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN) * 8);
+ }
+
+ error = alc_dma_alloc(sc);
+ if (error)
+ goto fail;
+
+ callout_init(&sc->sc_tick_ch, 0);
+ callout_setfunc(&sc->sc_tick_ch, alc_tick, sc);
+
+ /* Load station address. */
+ alc_get_macaddr(sc);
+
+ aprint_normal_dev(self, "Ethernet address %s\n",
+ ether_sprintf(sc->alc_eaddr));
+
+ ifp = &sc->sc_ec.ec_if;
+ ifp->if_softc = sc;
+ ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
+ ifp->if_init = alc_init;
+ ifp->if_ioctl = alc_ioctl;
+ ifp->if_start = alc_start;
+ ifp->if_stop = alc_stop;
+ ifp->if_watchdog = alc_watchdog;
+ ifp->if_baudrate = IF_Gbps(1);
+ IFQ_SET_MAXLEN(&ifp->if_snd, ALC_TX_RING_CNT - 1);
+ IFQ_SET_READY(&ifp->if_snd);
+ strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ);
+
+ sc->sc_ec.ec_capabilities = ETHERCAP_VLAN_MTU;
+
+#ifdef ALC_CHECKSUM
+ ifp->if_capabilities |= IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx |
+ IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx |
+ IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_TCPv4_Rx;
+#endif
+
+#if NVLAN > 0
+ sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_HWTAGGING;
+#endif
+
+ /* Set up MII bus. */
+ sc->sc_miibus.mii_ifp = ifp;
+ sc->sc_miibus.mii_readreg = alc_miibus_readreg;
+ sc->sc_miibus.mii_writereg = alc_miibus_writereg;
+ sc->sc_miibus.mii_statchg = alc_miibus_statchg;
+
+ sc->sc_ec.ec_mii = &sc->sc_miibus;
+ ifmedia_init(&sc->sc_miibus.mii_media, 0, alc_mediachange,
+ alc_mediastatus);
+ mii_flags = 0;
+ if ((sc->alc_flags & ALC_FLAG_JUMBO) != 0)
+ mii_flags |= MIIF_DOPAUSE;
+ mii_attach(self, &sc->sc_miibus, 0xffffffff, MII_PHY_ANY,
+ MII_OFFSET_ANY, mii_flags);
+
+ if (LIST_FIRST(&sc->sc_miibus.mii_phys) == NULL) {
+ printf("%s: no PHY found!\n", device_xname(sc->sc_dev));
+ ifmedia_add(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL,
+ 0, NULL);
+ ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL);
+ } else
+ ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_AUTO);
+
+ if_attach(ifp);
+ ether_ifattach(ifp, sc->alc_eaddr);
+
+ if (!pmf_device_register(self, NULL, NULL))
+ aprint_error_dev(self, "couldn't establish power handler\n");
+ else
+ pmf_class_network_register(self, ifp);
+
+ return;
+fail:
+ alc_dma_free(sc);
+ if (sc->sc_irq_handle != NULL) {
+ pci_intr_disestablish(sc->sc_pct, sc->sc_irq_handle);
+ sc->sc_irq_handle = NULL;
+ }
+ if (sc->sc_mem_size) {
+ bus_space_unmap(sc->sc_mem_bt, sc->sc_mem_bh, sc->sc_mem_size);
+ sc->sc_mem_size = 0;
+ }
+}
+
+static int
+alc_detach(device_t self, int flags)
+{
+ struct alc_softc *sc = device_private(self);
+ struct ifnet *ifp = &sc->sc_ec.ec_if;
+ int s;
+
+ s = splnet();
+ alc_stop(ifp, 0);
+ splx(s);
+
+ mii_detach(&sc->sc_miibus, MII_PHY_ANY, MII_OFFSET_ANY);
+
+ /* Delete all remaining media. */
+ ifmedia_delete_instance(&sc->sc_miibus.mii_media, IFM_INST_ANY);
+
+ ether_ifdetach(ifp);
+ if_detach(ifp);
+ alc_dma_free(sc);
+
+ alc_phy_down(sc);
+ if (sc->sc_irq_handle != NULL) {
+ pci_intr_disestablish(sc->sc_pct, sc->sc_irq_handle);
+ sc->sc_irq_handle = NULL;
+ }
+ if (sc->sc_mem_size) {
+ bus_space_unmap(sc->sc_mem_bt, sc->sc_mem_bh, sc->sc_mem_size);
+ sc->sc_mem_size = 0;
+ }
+
+ return (0);
+}
+
+static int
+alc_dma_alloc(struct alc_softc *sc)
+{
+ struct alc_txdesc *txd;
+ struct alc_rxdesc *rxd;
+ int nsegs, error, i;
+
+ /*
+ * Create DMA stuffs for TX ring
+ */
+ error = bus_dmamap_create(sc->sc_dmat, ALC_TX_RING_SZ, 1,
+ ALC_TX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->alc_cdata.alc_tx_ring_map);
+ if (error) {
+ sc->alc_cdata.alc_tx_ring_map = NULL;
+ return (ENOBUFS);
+ }
+
+ /* Allocate DMA'able memory for TX ring */
+ error = bus_dmamem_alloc(sc->sc_dmat, ALC_TX_RING_SZ,
+ ETHER_ALIGN, 0, &sc->alc_rdata.alc_tx_ring_seg, 1,
+ &nsegs, BUS_DMA_NOWAIT);
+ if (error) {
+ printf("%s: could not allocate DMA'able memory for Tx ring.\n",
+ device_xname(sc->sc_dev));
+ return error;
+ }
+
+ error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_tx_ring_seg,
+ nsegs, ALC_TX_RING_SZ, (void **)&sc->alc_rdata.alc_tx_ring,
+ BUS_DMA_NOWAIT);
+ if (error)
+ return (ENOBUFS);
+
+ /* Load the DMA map for Tx ring. */
+ error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map,
+ sc->alc_rdata.alc_tx_ring, ALC_TX_RING_SZ, NULL, BUS_DMA_WAITOK);
+ if (error) {
+ printf("%s: could not load DMA'able memory for Tx ring.\n",
+ device_xname(sc->sc_dev));
+ bus_dmamem_free(sc->sc_dmat,
+ &sc->alc_rdata.alc_tx_ring_seg, 1);
+ return error;
+ }
+
+ sc->alc_rdata.alc_tx_ring_paddr =
+ sc->alc_cdata.alc_tx_ring_map->dm_segs[0].ds_addr;
+
+ /*
+ * Create DMA stuffs for RX ring
+ */
+ error = bus_dmamap_create(sc->sc_dmat, ALC_RX_RING_SZ, 1,
+ ALC_RX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->alc_cdata.alc_rx_ring_map);
+ if (error)
+ return (ENOBUFS);
+
+ /* Allocate DMA'able memory for RX ring */
+ error = bus_dmamem_alloc(sc->sc_dmat, ALC_RX_RING_SZ,
+ ETHER_ALIGN, 0, &sc->alc_rdata.alc_rx_ring_seg, 1,
+ &nsegs, BUS_DMA_NOWAIT);
+ if (error) {
+ printf("%s: could not allocate DMA'able memory for Rx ring.\n",
+ device_xname(sc->sc_dev));
+ return error;
+ }
+
+ error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_rx_ring_seg,
+ nsegs, ALC_RX_RING_SZ, (void **)&sc->alc_rdata.alc_rx_ring,
+ BUS_DMA_NOWAIT);
+ if (error)
+ return (ENOBUFS);
+
+ /* Load the DMA map for Rx ring. */
+ error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map,
+ sc->alc_rdata.alc_rx_ring, ALC_RX_RING_SZ, NULL, BUS_DMA_WAITOK);
+ if (error) {
+ printf("%s: could not load DMA'able memory for Rx ring.\n",
+ device_xname(sc->sc_dev));
+ bus_dmamem_free(sc->sc_dmat,
+ (bus_dma_segment_t *)sc->alc_rdata.alc_rx_ring, 1);
+ return error;
+ }
+
+ sc->alc_rdata.alc_rx_ring_paddr =
+ sc->alc_cdata.alc_rx_ring_map->dm_segs[0].ds_addr;
+
+ /*
+ * Create DMA stuffs for RX return ring
+ */
+ error = bus_dmamap_create(sc->sc_dmat, ALC_RR_RING_SZ, 1,
+ ALC_RR_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->alc_cdata.alc_rr_ring_map);
+ if (error)
+ return (ENOBUFS);
+
+ /* Allocate DMA'able memory for RX return ring */
+ error = bus_dmamem_alloc(sc->sc_dmat, ALC_RR_RING_SZ,
+ ETHER_ALIGN, 0, &sc->alc_rdata.alc_rr_ring_seg, 1,
+ &nsegs, BUS_DMA_NOWAIT);
+ if (error) {
+ printf("%s: could not allocate DMA'able memory for Rx "
+ "return ring.\n", device_xname(sc->sc_dev));
+ return error;
+ }
+
+ error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_rr_ring_seg,
+ nsegs, ALC_RR_RING_SZ, (void **)&sc->alc_rdata.alc_rr_ring,
+ BUS_DMA_NOWAIT);
+ if (error)
+ return (ENOBUFS);
+
+ /* Load the DMA map for Rx return ring. */
+ error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map,
+ sc->alc_rdata.alc_rr_ring, ALC_RR_RING_SZ, NULL, BUS_DMA_WAITOK);
+ if (error) {
+ printf("%s: could not load DMA'able memory for Rx return ring."
+ "\n", device_xname(sc->sc_dev));
+ bus_dmamem_free(sc->sc_dmat,
+ (bus_dma_segment_t *)&sc->alc_rdata.alc_rr_ring, 1);
+ return error;
+ }
+
+ sc->alc_rdata.alc_rr_ring_paddr =
+ sc->alc_cdata.alc_rr_ring_map->dm_segs[0].ds_addr;
+
+ /*
+ * Create DMA stuffs for CMB block
+ */
+ error = bus_dmamap_create(sc->sc_dmat, ALC_CMB_SZ, 1,
+ ALC_CMB_SZ, 0, BUS_DMA_NOWAIT,
+ &sc->alc_cdata.alc_cmb_map);
+ if (error)
+ return (ENOBUFS);
+
+ /* Allocate DMA'able memory for CMB block */
+ error = bus_dmamem_alloc(sc->sc_dmat, ALC_CMB_SZ,
+ ETHER_ALIGN, 0, &sc->alc_rdata.alc_cmb_seg, 1,
+ &nsegs, BUS_DMA_NOWAIT);
+ if (error) {
+ printf("%s: could not allocate DMA'able memory for "
+ "CMB block\n", device_xname(sc->sc_dev));
+ return error;
+ }
+
+ error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_cmb_seg,
+ nsegs, ALC_CMB_SZ, (void **)&sc->alc_rdata.alc_cmb,
+ BUS_DMA_NOWAIT);
+ if (error)
+ return (ENOBUFS);
+
+ /* Load the DMA map for CMB block. */
+ error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_cmb_map,
+ sc->alc_rdata.alc_cmb, ALC_CMB_SZ, NULL,
+ BUS_DMA_WAITOK);
+ if (error) {
+ printf("%s: could not load DMA'able memory for CMB block\n",
+ device_xname(sc->sc_dev));
+ bus_dmamem_free(sc->sc_dmat,
+ (bus_dma_segment_t *)&sc->alc_rdata.alc_cmb, 1);
+ return error;
+ }
+
+ sc->alc_rdata.alc_cmb_paddr =
+ sc->alc_cdata.alc_cmb_map->dm_segs[0].ds_addr;
+
+ /*
+ * Create DMA stuffs for SMB block
+ */
+ error = bus_dmamap_create(sc->sc_dmat, ALC_SMB_SZ, 1,
+ ALC_SMB_SZ, 0, BUS_DMA_NOWAIT,
+ &sc->alc_cdata.alc_smb_map);
+ if (error)
+ return (ENOBUFS);
+
+ /* Allocate DMA'able memory for SMB block */
+ error = bus_dmamem_alloc(sc->sc_dmat, ALC_SMB_SZ,
+ ETHER_ALIGN, 0, &sc->alc_rdata.alc_smb_seg, 1,
+ &nsegs, BUS_DMA_NOWAIT);
+ if (error) {
+ printf("%s: could not allocate DMA'able memory for "
+ "SMB block\n", device_xname(sc->sc_dev));
+ return error;
+ }
+
+ error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_smb_seg,
+ nsegs, ALC_SMB_SZ, (void **)&sc->alc_rdata.alc_smb,
+ BUS_DMA_NOWAIT);
+ if (error)
+ return (ENOBUFS);
+
+ /* Load the DMA map for SMB block */
+ error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_smb_map,
+ sc->alc_rdata.alc_smb, ALC_SMB_SZ, NULL,
+ BUS_DMA_WAITOK);
+ if (error) {
+ printf("%s: could not load DMA'able memory for SMB block\n",
+ device_xname(sc->sc_dev));
+ bus_dmamem_free(sc->sc_dmat,
+ (bus_dma_segment_t *)&sc->alc_rdata.alc_smb, 1);
+ return error;
+ }
+
+ sc->alc_rdata.alc_smb_paddr =
+ sc->alc_cdata.alc_smb_map->dm_segs[0].ds_addr;
+
+
+ /* Create DMA maps for Tx buffers. */
+ for (i = 0; i < ALC_TX_RING_CNT; i++) {
+ txd = &sc->alc_cdata.alc_txdesc[i];
+ txd->tx_m = NULL;
+ txd->tx_dmamap = NULL;
+ error = bus_dmamap_create(sc->sc_dmat, ALC_TSO_MAXSIZE,
+ ALC_MAXTXSEGS, ALC_TSO_MAXSEGSIZE, 0, BUS_DMA_NOWAIT,
+ &txd->tx_dmamap);
+ if (error) {
+ printf("%s: could not create Tx dmamap.\n",
+ device_xname(sc->sc_dev));
+ return error;
+ }
+ }
+
+ /* Create DMA maps for Rx buffers. */
+ error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0,
+ BUS_DMA_NOWAIT, &sc->alc_cdata.alc_rx_sparemap);
+ if (error) {
+ printf("%s: could not create spare Rx dmamap.\n",
+ device_xname(sc->sc_dev));
+ return error;
+ }
+
+ for (i = 0; i < ALC_RX_RING_CNT; i++) {
+ rxd = &sc->alc_cdata.alc_rxdesc[i];
+ rxd->rx_m = NULL;
+ rxd->rx_dmamap = NULL;
+ error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1,
+ MCLBYTES, 0, BUS_DMA_NOWAIT, &rxd->rx_dmamap);
+ if (error) {
+ printf("%s: could not create Rx dmamap.\n",
+ device_xname(sc->sc_dev));
+ return error;
+ }
+ }
+
+ return (0);
+}
+
+
+static void
+alc_dma_free(struct alc_softc *sc)
+{
+ struct alc_txdesc *txd;
+ struct alc_rxdesc *rxd;
+ int i;
+
+ /* Tx buffers */
+ for (i = 0; i < ALC_TX_RING_CNT; i++) {
+ txd = &sc->alc_cdata.alc_txdesc[i];
+ if (txd->tx_dmamap != NULL) {
+ bus_dmamap_destroy(sc->sc_dmat, txd->tx_dmamap);
+ txd->tx_dmamap = NULL;
+ }
+ }
+ /* Rx buffers */
+ for (i = 0; i < ALC_RX_RING_CNT; i++) {
+ rxd = &sc->alc_cdata.alc_rxdesc[i];
+ if (rxd->rx_dmamap != NULL) {
+ bus_dmamap_destroy(sc->sc_dmat, rxd->rx_dmamap);
+ rxd->rx_dmamap = NULL;
+ }
+ }
+ if (sc->alc_cdata.alc_rx_sparemap != NULL) {
+ bus_dmamap_destroy(sc->sc_dmat, sc->alc_cdata.alc_rx_sparemap);
+ sc->alc_cdata.alc_rx_sparemap = NULL;
+ }
+
+ /* Tx ring. */
+ if (sc->alc_cdata.alc_tx_ring_map != NULL)
+ bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map);
+ if (sc->alc_cdata.alc_tx_ring_map != NULL &&
+ sc->alc_rdata.alc_tx_ring != NULL)
+ bus_dmamem_free(sc->sc_dmat,
+ (bus_dma_segment_t *)sc->alc_rdata.alc_tx_ring, 1);
+ sc->alc_rdata.alc_tx_ring = NULL;
+ sc->alc_cdata.alc_tx_ring_map = NULL;
+
+ /* Rx ring. */
+ if (sc->alc_cdata.alc_rx_ring_map != NULL)
+ bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map);
+ if (sc->alc_cdata.alc_rx_ring_map != NULL &&
+ sc->alc_rdata.alc_rx_ring != NULL)
+ bus_dmamem_free(sc->sc_dmat,
+ (bus_dma_segment_t *)sc->alc_rdata.alc_rx_ring, 1);
+ sc->alc_rdata.alc_rx_ring = NULL;
+ sc->alc_cdata.alc_rx_ring_map = NULL;
+
+ /* Rx return ring. */
+ if (sc->alc_cdata.alc_rr_ring_map != NULL)
+ bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map);
+ if (sc->alc_cdata.alc_rr_ring_map != NULL &&
+ sc->alc_rdata.alc_rr_ring != NULL)
+ bus_dmamem_free(sc->sc_dmat,
+ (bus_dma_segment_t *)sc->alc_rdata.alc_rr_ring, 1);
+ sc->alc_rdata.alc_rr_ring = NULL;
+ sc->alc_cdata.alc_rr_ring_map = NULL;
+
+ /* CMB block */
+ if (sc->alc_cdata.alc_cmb_map != NULL)
+ bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_cmb_map);
+ if (sc->alc_cdata.alc_cmb_map != NULL &&
+ sc->alc_rdata.alc_cmb != NULL)
+ bus_dmamem_free(sc->sc_dmat,
+ (bus_dma_segment_t *)sc->alc_rdata.alc_cmb, 1);
+ sc->alc_rdata.alc_cmb = NULL;
+ sc->alc_cdata.alc_cmb_map = NULL;
+
+ /* SMB block */
+ if (sc->alc_cdata.alc_smb_map != NULL)
+ bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_smb_map);
+ if (sc->alc_cdata.alc_smb_map != NULL &&
+ sc->alc_rdata.alc_smb != NULL)
+ bus_dmamem_free(sc->sc_dmat,
+ (bus_dma_segment_t *)sc->alc_rdata.alc_smb, 1);
+ sc->alc_rdata.alc_smb = NULL;
+ sc->alc_cdata.alc_smb_map = NULL;
+}
+
+static int
+alc_encap(struct alc_softc *sc, struct mbuf **m_head)
+{
+ struct alc_txdesc *txd, *txd_last;
+ struct tx_desc *desc;
+ struct mbuf *m;
+ bus_dmamap_t map;
+ uint32_t cflags, poff, vtag;
+ int error, idx, nsegs, prod;
+#if NVLAN > 0
+ struct m_tag *mtag;
+#endif
+
+ m = *m_head;
+ cflags = vtag = 0;
+ poff = 0;
+
+ prod = sc->alc_cdata.alc_tx_prod;
+ txd = &sc->alc_cdata.alc_txdesc[prod];
+ txd_last = txd;
+ map = txd->tx_dmamap;
+
+ error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, BUS_DMA_NOWAIT);
+
+ if (error == EFBIG) {
+ error = 0;
+
+ *m_head = m_pullup(*m_head, MHLEN);
+ if (*m_head == NULL) {
+ printf("%s: can't defrag TX mbuf\n",
+ device_xname(sc->sc_dev));
+ return ENOBUFS;
+ }
+
+ error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head,
+ BUS_DMA_NOWAIT);
+
+ if (error != 0) {
+ printf("%s: could not load defragged TX mbuf\n",
+ device_xname(sc->sc_dev));
+ m_freem(*m_head);
+ *m_head = NULL;
+ return error;
+ }
+ } else if (error) {
+ printf("%s: could not load TX mbuf\n",
device_xname(sc->sc_dev));
+ return (error);
+ }
+
+ nsegs = map->dm_nsegs;
+
+ if (nsegs == 0) {
+ m_freem(*m_head);
+ *m_head = NULL;
+ return (EIO);
+ }
+
+ /* Check descriptor overrun. */
+ if (sc->alc_cdata.alc_tx_cnt + nsegs >= ALC_TX_RING_CNT - 3) {
+ bus_dmamap_unload(sc->sc_dmat, map);
+ return (ENOBUFS);
+ }
+ bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize,
+ BUS_DMASYNC_PREWRITE);
+
+ m = *m_head;
+ desc = NULL;
+ idx = 0;
+#if NVLAN > 0
+ /* Configure VLAN hardware tag insertion. */
+ if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ec, m))) {
+ vtag = htons(VLAN_TAG_VALUE(mtag));
+ vtag = (vtag << TD_VLAN_SHIFT) & TD_VLAN_MASK;
+ cflags |= TD_INS_VLAN_TAG;
+ }
+#endif
+ /* Configure Tx checksum offload. */
+ if ((m->m_pkthdr.csum_flags & ALC_CSUM_FEATURES) != 0) {
+ cflags |= TD_CUSTOM_CSUM;
+ /* Set checksum start offset. */
+ cflags |= ((poff >> 1) << TD_PLOAD_OFFSET_SHIFT) &
+ TD_PLOAD_OFFSET_MASK;
+ }
+ for (; idx < nsegs; idx++) {
+ desc = &sc->alc_rdata.alc_tx_ring[prod];
+ desc->len =
+ htole32(TX_BYTES(map->dm_segs[idx].ds_len) | vtag);
+ desc->flags = htole32(cflags);
+ desc->addr = htole64(map->dm_segs[idx].ds_addr);
+ sc->alc_cdata.alc_tx_cnt++;
+ ALC_DESC_INC(prod, ALC_TX_RING_CNT);
+ }
+ /* Update producer index. */
+ sc->alc_cdata.alc_tx_prod = prod;
+
+ /* Finally set EOP on the last descriptor. */
+ prod = (prod + ALC_TX_RING_CNT - 1) % ALC_TX_RING_CNT;
+ desc = &sc->alc_rdata.alc_tx_ring[prod];
+ desc->flags |= htole32(TD_EOP);
+
+ /* Swap dmamap of the first and the last. */
+ txd = &sc->alc_cdata.alc_txdesc[prod];
+ map = txd_last->tx_dmamap;
+ txd_last->tx_dmamap = txd->tx_dmamap;
+ txd->tx_dmamap = map;
+ txd->tx_m = m;
+
+ return (0);
+}
+
+static void
+alc_start(struct ifnet *ifp)
+{
+ struct alc_softc *sc = ifp->if_softc;
+ struct mbuf *m_head;
+ int enq;
+
+ if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
+ return;
+
+ /* Reclaim transmitted frames. */
+ if (sc->alc_cdata.alc_tx_cnt >= ALC_TX_DESC_HIWAT)
+ alc_txeof(sc);
+
+ enq = 0;
+ for (;;) {
+ IFQ_DEQUEUE(&ifp->if_snd, m_head);
+ if (m_head == NULL)
+ break;
+
+ /*
+ * Pack the data into the transmit ring. If we
+ * don't have room, set the OACTIVE flag and wait
+ * for the NIC to drain the ring.
+ */
+ if (alc_encap(sc, &m_head)) {
+ if (m_head == NULL)
+ break;
+ ifp->if_flags |= IFF_OACTIVE;
+ break;
+ }
+ enq = 1;
+
+#if NBPFILTER > 0
+ /*
+ * If there's a BPF listener, bounce a copy of this frame
+ * to him.
+ */
+ if (ifp->if_bpf != NULL)
+ bpf_mtap_ether(ifp->if_bpf, m_head, BPF_DIRECTION_OUT);
+#endif
+ }
+
+ if (enq) {
+ /* Sync descriptors. */
+ bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 0,
+ sc->alc_cdata.alc_tx_ring_map->dm_mapsize,
+ BUS_DMASYNC_PREWRITE);
+ /* Kick. Assume we're using normal Tx priority queue. */
+ CSR_WRITE_4(sc, ALC_MBOX_TD_PROD_IDX,
+ (sc->alc_cdata.alc_tx_prod <<
+ MBOX_TD_PROD_LO_IDX_SHIFT) &
+ MBOX_TD_PROD_LO_IDX_MASK);
+ /* Set a timeout in case the chip goes out to lunch. */
+ ifp->if_timer = ALC_TX_TIMEOUT;
+ }
+}
+
+static void
+alc_watchdog(struct ifnet *ifp)
+{
+ struct alc_softc *sc = ifp->if_softc;
+
+ if ((sc->alc_flags & ALC_FLAG_LINK) == 0) {
+ printf("%s: watchdog timeout (missed link)\n",
+ device_xname(sc->sc_dev));
+ ifp->if_oerrors++;
+ alc_init(ifp);
+ return;
+ }
+
+ printf("%s: watchdog timeout\n", device_xname(sc->sc_dev));
+ ifp->if_oerrors++;
+ alc_init(ifp);
+
+ if (!IFQ_IS_EMPTY(&ifp->if_snd))
+ alc_start(ifp);
+}
+
+static int
+alc_ioctl(struct ifnet *ifp, u_long cmd, void *data)
+{
+ struct alc_softc *sc = ifp->if_softc;
+ int s, error = 0;
+
+ s = splnet();
+
+ error = ether_ioctl(ifp, cmd, data);
+ if (error == ENETRESET) {
+ if (ifp->if_flags & IFF_RUNNING)
+ alc_iff(sc);
+ error = 0;
+ }
+
+ splx(s);
+ return (error);
+}
+
+static void
+alc_mac_config(struct alc_softc *sc)
+{
+ struct mii_data *mii;
+ uint32_t reg;
+
+ mii = &sc->sc_miibus;
+ reg = CSR_READ_4(sc, ALC_MAC_CFG);
+ reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC |
+ MAC_CFG_SPEED_MASK);
+ /* Reprogram MAC with resolved speed/duplex. */
+ switch (IFM_SUBTYPE(mii->mii_media_active)) {
+ case IFM_10_T:
+ case IFM_100_TX:
+ reg |= MAC_CFG_SPEED_10_100;
+ break;
+ case IFM_1000_T:
+ reg |= MAC_CFG_SPEED_1000;
+ break;
+ }
+ if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
+ reg |= MAC_CFG_FULL_DUPLEX;
+ if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
+ reg |= MAC_CFG_TX_FC;
+ if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
+ reg |= MAC_CFG_RX_FC;
+ }
+ CSR_WRITE_4(sc, ALC_MAC_CFG, reg);
+}
+
+static void
+alc_stats_clear(struct alc_softc *sc)
+{
+ struct smb sb, *smb;
+ uint32_t *reg;
+ int i;
+
+ if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) {
+ bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0,
+ sc->alc_cdata.alc_smb_map->dm_mapsize,
+ BUS_DMASYNC_POSTREAD);
+ smb = sc->alc_rdata.alc_smb;
+ /* Update done, clear. */
+ smb->updated = 0;
+ bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0,
+ sc->alc_cdata.alc_smb_map->dm_mapsize,
+ BUS_DMASYNC_PREWRITE);
+ } else {
+ for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered;
+ reg++) {
+ CSR_READ_4(sc, ALC_RX_MIB_BASE + i);
+ i += sizeof(uint32_t);
+ }
+ /* Read Tx statistics. */
+ for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes;
+ reg++) {
+ CSR_READ_4(sc, ALC_TX_MIB_BASE + i);
+ i += sizeof(uint32_t);
+ }
+ }
+}
+
+static void
+alc_stats_update(struct alc_softc *sc)
+{
+ struct ifnet *ifp = &sc->sc_ec.ec_if;
+ struct alc_hw_stats *stat;
+ struct smb sb, *smb;
+ uint32_t *reg;
+ int i;
+
+ stat = &sc->alc_stats;
+ if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) {
+ bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0,
+ sc->alc_cdata.alc_smb_map->dm_mapsize,
+ BUS_DMASYNC_POSTREAD);
+ smb = sc->alc_rdata.alc_smb;
+ if (smb->updated == 0)
+ return;
+ } else {
+ smb = &sb;
+ /* Read Rx statistics. */
+ for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered;
+ reg++) {
+ *reg = CSR_READ_4(sc, ALC_RX_MIB_BASE + i);
+ i += sizeof(uint32_t);
+ }
+ /* Read Tx statistics. */
+ for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes;
+ reg++) {
+ *reg = CSR_READ_4(sc, ALC_TX_MIB_BASE + i);
+ i += sizeof(uint32_t);
+ }
+ }
+
+ /* Rx stats. */
+ stat->rx_frames += smb->rx_frames;
+ stat->rx_bcast_frames += smb->rx_bcast_frames;
+ stat->rx_mcast_frames += smb->rx_mcast_frames;
+ stat->rx_pause_frames += smb->rx_pause_frames;
+ stat->rx_control_frames += smb->rx_control_frames;
+ stat->rx_crcerrs += smb->rx_crcerrs;
+ stat->rx_lenerrs += smb->rx_lenerrs;
+ stat->rx_bytes += smb->rx_bytes;
+ stat->rx_runts += smb->rx_runts;
+ stat->rx_fragments += smb->rx_fragments;
+ stat->rx_pkts_64 += smb->rx_pkts_64;
+ stat->rx_pkts_65_127 += smb->rx_pkts_65_127;
+ stat->rx_pkts_128_255 += smb->rx_pkts_128_255;
+ stat->rx_pkts_256_511 += smb->rx_pkts_256_511;
+ stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023;
+ stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518;
+ stat->rx_pkts_1519_max += smb->rx_pkts_1519_max;
+ stat->rx_pkts_truncated += smb->rx_pkts_truncated;
+ stat->rx_fifo_oflows += smb->rx_fifo_oflows;
+ stat->rx_rrs_errs += smb->rx_rrs_errs;
+ stat->rx_alignerrs += smb->rx_alignerrs;
+ stat->rx_bcast_bytes += smb->rx_bcast_bytes;
+ stat->rx_mcast_bytes += smb->rx_mcast_bytes;
+ stat->rx_pkts_filtered += smb->rx_pkts_filtered;
+
+ /* Tx stats. */
+ stat->tx_frames += smb->tx_frames;
+ stat->tx_bcast_frames += smb->tx_bcast_frames;
+ stat->tx_mcast_frames += smb->tx_mcast_frames;
+ stat->tx_pause_frames += smb->tx_pause_frames;
+ stat->tx_excess_defer += smb->tx_excess_defer;
+ stat->tx_control_frames += smb->tx_control_frames;
+ stat->tx_deferred += smb->tx_deferred;
+ stat->tx_bytes += smb->tx_bytes;
+ stat->tx_pkts_64 += smb->tx_pkts_64;
+ stat->tx_pkts_65_127 += smb->tx_pkts_65_127;
+ stat->tx_pkts_128_255 += smb->tx_pkts_128_255;
+ stat->tx_pkts_256_511 += smb->tx_pkts_256_511;
+ stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023;
+ stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518;
+ stat->tx_pkts_1519_max += smb->tx_pkts_1519_max;
+ stat->tx_single_colls += smb->tx_single_colls;
+ stat->tx_multi_colls += smb->tx_multi_colls;
+ stat->tx_late_colls += smb->tx_late_colls;
+ stat->tx_excess_colls += smb->tx_excess_colls;
+ stat->tx_abort += smb->tx_abort;
+ stat->tx_underrun += smb->tx_underrun;
+ stat->tx_desc_underrun += smb->tx_desc_underrun;
+ stat->tx_lenerrs += smb->tx_lenerrs;
+ stat->tx_pkts_truncated += smb->tx_pkts_truncated;
+ stat->tx_bcast_bytes += smb->tx_bcast_bytes;
+ stat->tx_mcast_bytes += smb->tx_mcast_bytes;
+
+ /* Update counters in ifnet. */
+ ifp->if_opackets += smb->tx_frames;
+
+ ifp->if_collisions += smb->tx_single_colls +
+ smb->tx_multi_colls * 2 + smb->tx_late_colls +
+ smb->tx_abort * HDPX_CFG_RETRY_DEFAULT;
+
+ /*
+ * XXX
+ * tx_pkts_truncated counter looks suspicious. It constantly
+ * increments with no sign of Tx errors. This may indicate
+ * the counter name is not correct one so I've removed the
+ * counter in output errors.
+ */
+ ifp->if_oerrors += smb->tx_abort + smb->tx_late_colls +
+ smb->tx_underrun;
+
+ ifp->if_ipackets += smb->rx_frames;
+
+ ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs +
+ smb->rx_runts + smb->rx_pkts_truncated +
+ smb->rx_fifo_oflows + smb->rx_rrs_errs +
+ smb->rx_alignerrs;
+
+ if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) {
+ /* Update done, clear. */
+ smb->updated = 0;
+ bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0,
+ sc->alc_cdata.alc_smb_map->dm_mapsize, BUS_DMASYNC_PREWRITE);
+ }
+}
+
+static int
+alc_intr(void *arg)
+{
+ struct alc_softc *sc = arg;
+ struct ifnet *ifp = &sc->sc_ec.ec_if;
+ uint32_t status;
+
+ status = CSR_READ_4(sc, ALC_INTR_STATUS);
+ if ((status & ALC_INTRS) == 0)
+ return (0);
+
+ /* Acknowledge and disable interrupts. */
+ CSR_WRITE_4(sc, ALC_INTR_STATUS, status | INTR_DIS_INT);
+
+ if (ifp->if_flags & IFF_RUNNING) {
+ if (status & INTR_RX_PKT) {
+ int error;
+
+ error = alc_rxintr(sc);
+ if (error) {
+ alc_init(ifp);
+ return (0);
+ }
+ }
+
+ if (status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST |
+ INTR_TXQ_TO_RST)) {
+ if (status & INTR_DMA_RD_TO_RST)
+ printf("%s: DMA read error! -- resetting\n",
+ device_xname(sc->sc_dev));
+ if (status & INTR_DMA_WR_TO_RST)
+ printf("%s: DMA write error! -- resetting\n",
+ device_xname(sc->sc_dev));
+ if (status & INTR_TXQ_TO_RST)
+ printf("%s: TxQ reset! -- resetting\n",
+ device_xname(sc->sc_dev));
+ alc_init(ifp);
+ return (0);
+ }
+
+ alc_txeof(sc);
+ if (!IFQ_IS_EMPTY(&ifp->if_snd))
+ alc_start(ifp);
+ }
+
+ /* Re-enable interrupts. */
+ CSR_WRITE_4(sc, ALC_INTR_STATUS, 0x7FFFFFFF);
+ return (1);
+}
+
+static void
+alc_txeof(struct alc_softc *sc)
+{
+ struct ifnet *ifp = &sc->sc_ec.ec_if;
+ struct alc_txdesc *txd;
+ uint32_t cons, prod;
+ int prog;
+
+ if (sc->alc_cdata.alc_tx_cnt == 0)
+ return;
+ bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 0,
+ sc->alc_cdata.alc_tx_ring_map->dm_mapsize,
+ BUS_DMASYNC_POSTREAD);
+ if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) {
+ bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_cmb_map, 0,
+ sc->alc_cdata.alc_cmb_map->dm_mapsize,
+ BUS_DMASYNC_POSTREAD);
+ prod = sc->alc_rdata.alc_cmb->cons;
+ } else
+ prod = CSR_READ_4(sc, ALC_MBOX_TD_CONS_IDX);
+ /* Assume we're using normal Tx priority queue. */
+ prod = (prod & MBOX_TD_CONS_LO_IDX_MASK) >>
+ MBOX_TD_CONS_LO_IDX_SHIFT;
+ cons = sc->alc_cdata.alc_tx_cons;
+ /*
+ * Go through our Tx list and free mbufs for those
+ * frames which have been transmitted.
+ */
+ for (prog = 0; cons != prod; prog++,
+ ALC_DESC_INC(cons, ALC_TX_RING_CNT)) {
+ if (sc->alc_cdata.alc_tx_cnt <= 0)
+ break;
+ prog++;
+ ifp->if_flags &= ~IFF_OACTIVE;
+ sc->alc_cdata.alc_tx_cnt--;
+ txd = &sc->alc_cdata.alc_txdesc[cons];
+ if (txd->tx_m != NULL) {
+ /* Reclaim transmitted mbufs. */
+ bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap);
+ m_freem(txd->tx_m);
+ txd->tx_m = NULL;
+ }
+ }
+
+ if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0)
+ bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_cmb_map, 0,
+ sc->alc_cdata.alc_cmb_map->dm_mapsize, BUS_DMASYNC_PREWRITE);
+ sc->alc_cdata.alc_tx_cons = cons;
+ /*
+ * Unarm watchdog timer only when there is no pending
+ * frames in Tx queue.
+ */
+ if (sc->alc_cdata.alc_tx_cnt == 0)
+ ifp->if_timer = 0;
+}
+
+static int
+alc_newbuf(struct alc_softc *sc, struct alc_rxdesc *rxd, int init)
+{
+ struct mbuf *m;
+ bus_dmamap_t map;
+ int error;
+
+ MGETHDR(m, init ? M_WAITOK : M_DONTWAIT, MT_DATA);
+ if (m == NULL)
+ return (ENOBUFS);
+ MCLGET(m, init ? M_WAITOK : M_DONTWAIT);
+ if (!(m->m_flags & M_EXT)) {
+ m_freem(m);
+ return (ENOBUFS);
+ }
+
+ m->m_len = m->m_pkthdr.len = RX_BUF_SIZE_MAX;
+
+ error = bus_dmamap_load_mbuf(sc->sc_dmat,
+ sc->alc_cdata.alc_rx_sparemap, m, BUS_DMA_NOWAIT);
+
+ if (error != 0) {
+ if (!error) {
+ bus_dmamap_unload(sc->sc_dmat,
+ sc->alc_cdata.alc_rx_sparemap);
+ error = EFBIG;
+ printf("%s: too many segments?!\n",
+ device_xname(sc->sc_dev));
+ }
+ m_freem(m);
+
+ if (init)
+ printf("%s: can't load RX mbuf\n",
device_xname(sc->sc_dev));
+
+ return (error);
+ }
+
+ if (rxd->rx_m != NULL) {
+ bus_dmamap_sync(sc->sc_dmat, rxd->rx_dmamap, 0,
+ rxd->rx_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD);
+ bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap);
+ }
+ map = rxd->rx_dmamap;
+ rxd->rx_dmamap = sc->alc_cdata.alc_rx_sparemap;
+ sc->alc_cdata.alc_rx_sparemap = map;
+ rxd->rx_m = m;
+ rxd->rx_desc->addr = htole64(rxd->rx_dmamap->dm_segs[0].ds_addr);
+ return (0);
+}
+
+static int
+alc_rxintr(struct alc_softc *sc)
+{
+ struct ifnet *ifp = &sc->sc_ec.ec_if;
+ struct rx_rdesc *rrd;
+ uint32_t nsegs, status;
+ int rr_cons, prog;
+
+ bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map, 0,
+ sc->alc_cdata.alc_rr_ring_map->dm_mapsize, BUS_DMASYNC_POSTREAD);
+ bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map, 0,
+ sc->alc_cdata.alc_rx_ring_map->dm_mapsize, BUS_DMASYNC_POSTREAD);
+ rr_cons = sc->alc_cdata.alc_rr_cons;
+ for (prog = 0; (ifp->if_flags & IFF_RUNNING) != 0;) {
+ rrd = &sc->alc_rdata.alc_rr_ring[rr_cons];
+ status = le32toh(rrd->status);
+ if ((status & RRD_VALID) == 0)
+ break;
+ nsegs = RRD_RD_CNT(le32toh(rrd->rdinfo));
+ if (nsegs == 0) {
+ /* This should not happen! */
+ if (alcdebug)
+ printf("%s: unexpected segment count -- "
+ "resetting\n", device_xname(sc->sc_dev));
+ return (EIO);
+ }
+ alc_rxeof(sc, rrd);
+ /* Clear Rx return status. */
+ rrd->status = 0;
+ ALC_DESC_INC(rr_cons, ALC_RR_RING_CNT);
+ sc->alc_cdata.alc_rx_cons += nsegs;
+ sc->alc_cdata.alc_rx_cons %= ALC_RR_RING_CNT;
+ prog += nsegs;
+ }
+
+ if (prog > 0) {
+ /* Update the consumer index. */
+ sc->alc_cdata.alc_rr_cons = rr_cons;
+ /* Sync Rx return descriptors. */
+ bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map, 0,
+ sc->alc_cdata.alc_rr_ring_map->dm_mapsize,
+ BUS_DMASYNC_PREWRITE);
+ /*
+ * Sync updated Rx descriptors such that controller see
+ * modified buffer addresses.
+ */
+ bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map, 0,
+ sc->alc_cdata.alc_rx_ring_map->dm_mapsize,
+ BUS_DMASYNC_PREWRITE);
+ /*
+ * Let controller know availability of new Rx buffers.
+ * Since alc(4) use RXQ_CFG_RD_BURST_DEFAULT descriptors
+ * it may be possible to update ALC_MBOX_RD0_PROD_IDX
+ * only when Rx buffer pre-fetching is required. In
+ * addition we already set ALC_RX_RD_FREE_THRESH to
+ * RX_RD_FREE_THRESH_LO_DEFAULT descriptors. However
+ * it still seems that pre-fetching needs more
+ * experimentation.
+ */
+ CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX,
+ sc->alc_cdata.alc_rx_cons);
+ }
+
+ return (0);
+}
+
+/* Receive a frame. */
+static void
+alc_rxeof(struct alc_softc *sc, struct rx_rdesc *rrd)
+{
+ struct ifnet *ifp = &sc->sc_ec.ec_if;
+ struct alc_rxdesc *rxd;
+ struct mbuf *mp, *m;
+ uint32_t rdinfo, status;
+ int count, nsegs, rx_cons;
+
+ status = le32toh(rrd->status);
+ rdinfo = le32toh(rrd->rdinfo);
+ rx_cons = RRD_RD_IDX(rdinfo);
+ nsegs = RRD_RD_CNT(rdinfo);
+
+ sc->alc_cdata.alc_rxlen = RRD_BYTES(status);
+ if (status & (RRD_ERR_SUM | RRD_ERR_LENGTH)) {
+ /*
+ * We want to pass the following frames to upper
+ * layer regardless of error status of Rx return
+ * ring.
+ *
+ * o IP/TCP/UDP checksum is bad.
+ * o frame length and protocol specific length
+ * does not match.
+ *
+ * Force network stack compute checksum for
+ * errored frames.
+ */
+ status |= RRD_TCP_UDPCSUM_NOK | RRD_IPCSUM_NOK;
+ if ((RRD_ERR_CRC | RRD_ERR_ALIGN | RRD_ERR_TRUNC |
+ RRD_ERR_RUNT) != 0)
+ return;
+ }
+
+ for (count = 0; count < nsegs; count++,
+ ALC_DESC_INC(rx_cons, ALC_RX_RING_CNT)) {
+ rxd = &sc->alc_cdata.alc_rxdesc[rx_cons];
+ mp = rxd->rx_m;
+ /* Add a new receive buffer to the ring. */
+ if (alc_newbuf(sc, rxd, 0) != 0) {
+ ifp->if_iqdrops++;
+ /* Reuse Rx buffers. */
+ if (sc->alc_cdata.alc_rxhead != NULL)
+ m_freem(sc->alc_cdata.alc_rxhead);
+ break;
+ }
+
+ /*
+ * Assume we've received a full sized frame.
+ * Actual size is fixed when we encounter the end of
+ * multi-segmented frame.
+ */
+ mp->m_len = sc->alc_buf_size;
+
+ /* Chain received mbufs. */
+ if (sc->alc_cdata.alc_rxhead == NULL) {
+ sc->alc_cdata.alc_rxhead = mp;
+ sc->alc_cdata.alc_rxtail = mp;
+ } else {
+ mp->m_flags &= ~M_PKTHDR;
+ sc->alc_cdata.alc_rxprev_tail =
+ sc->alc_cdata.alc_rxtail;
+ sc->alc_cdata.alc_rxtail->m_next = mp;
+ sc->alc_cdata.alc_rxtail = mp;
+ }
+
+ if (count == nsegs - 1) {
+ /* Last desc. for this frame. */
+ m = sc->alc_cdata.alc_rxhead;
+ m->m_flags |= M_PKTHDR;
+ /*
+ * It seems that L1C/L2C controller has no way
+ * to tell hardware to strip CRC bytes.
+ */
+ m->m_pkthdr.len =
+ sc->alc_cdata.alc_rxlen - ETHER_CRC_LEN;
+ if (nsegs > 1) {
+ /* Set last mbuf size. */
+ mp->m_len = sc->alc_cdata.alc_rxlen -
+ (nsegs - 1) * sc->alc_buf_size;
+ /* Remove the CRC bytes in chained mbufs. */
+ if (mp->m_len <= ETHER_CRC_LEN) {
+ sc->alc_cdata.alc_rxtail =
+ sc->alc_cdata.alc_rxprev_tail;
+ sc->alc_cdata.alc_rxtail->m_len -=
+ (ETHER_CRC_LEN - mp->m_len);
+ sc->alc_cdata.alc_rxtail->m_next = NULL;
+ m_freem(mp);
+ } else {
+ mp->m_len -= ETHER_CRC_LEN;
+ }
+ } else
+ m->m_len = m->m_pkthdr.len;
+ m->m_pkthdr.rcvif = ifp;
+#if NVLAN > 0
+ /*
+ * Due to hardware bugs, Rx checksum offloading
+ * was intentionally disabled.
+ */
+ if (status & RRD_VLAN_TAG) {
+ u_int32_t vtag = RRD_VLAN(le32toh(rrd->vtag));
+ VLAN_INPUT_TAG(ifp, m, ntohs(vtag), );
+ }
+#endif
+
+#if NBPFILTER > 0
+ if (ifp->if_bpf)
+ bpf_mtap_ether(ifp->if_bpf, m,
+ BPF_DIRECTION_IN);
+#endif
+
+ {
+ /* Pass it on. */
+ ether_input(ifp, m);
+ }
+ }
+ }
+ /* Reset mbuf chains. */
+ ALC_RXCHAIN_RESET(sc);
+}
+
+static void
+alc_tick(void *xsc)
+{
+ struct alc_softc *sc = xsc;
+ struct mii_data *mii = &sc->sc_miibus;
+ int s;
+
+ s = splnet();
+ mii_tick(mii);
+ alc_stats_update(sc);
+ splx(s);
+
+ callout_schedule(&sc->sc_tick_ch, hz);
+}
+
+static void
+alc_reset(struct alc_softc *sc)
+{
+ uint32_t reg;
+ int i;
+
+ CSR_WRITE_4(sc, ALC_MASTER_CFG, MASTER_RESET);
+ for (i = ALC_RESET_TIMEOUT; i > 0; i--) {
+ DELAY(10);
+ if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_RESET) == 0)
+ break;
+ }
+ if (i == 0)
+ printf("%s: master reset timeout!\n", device_xname(sc->sc_dev));
+
+ for (i = ALC_RESET_TIMEOUT; i > 0; i--) {
+ if ((reg = CSR_READ_4(sc, ALC_IDLE_STATUS)) == 0)
+ break;
+ DELAY(10);
+ }
+
+ if (i == 0)
+ printf("%s: reset timeout(0x%08x)!\n",
device_xname(sc->sc_dev),
+ reg);
+}
+
+static int
+alc_init(struct ifnet *ifp)
+{
+ struct alc_softc *sc = ifp->if_softc;
+ struct mii_data *mii;
+ uint8_t eaddr[ETHER_ADDR_LEN];
+ bus_addr_t paddr;
+ uint32_t reg, rxf_hi, rxf_lo;
+ int error;
+
+ /*
+ * Cancel any pending I/O.
+ */
+ alc_stop(ifp, 0);
+ /*
+ * Reset the chip to a known state.
+ */
+ alc_reset(sc);
+
+ /* Initialize Rx descriptors. */
+ error = alc_init_rx_ring(sc);
+ if (error != 0) {
+ printf("%s: no memory for Rx buffers.\n",
device_xname(sc->sc_dev));
+ alc_stop(ifp, 0);
+ return (error);
+ }
+ alc_init_rr_ring(sc);
+ alc_init_tx_ring(sc);
+ alc_init_cmb(sc);
+ alc_init_smb(sc);
+
+ /* Reprogram the station address. */
+ memcpy(eaddr, CLLADDR(ifp->if_sadl), sizeof(eaddr));
+ CSR_WRITE_4(sc, ALC_PAR0,
+ eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]);
+ CSR_WRITE_4(sc, ALC_PAR1, eaddr[0] << 8 | eaddr[1]);
+ /*
+ * Clear WOL status and disable all WOL feature as WOL
+ * would interfere Rx operation under normal environments.
+ */
+ CSR_READ_4(sc, ALC_WOL_CFG);
+ CSR_WRITE_4(sc, ALC_WOL_CFG, 0);
+ /* Set Tx descriptor base addresses. */
+ paddr = sc->alc_rdata.alc_tx_ring_paddr;
+ CSR_WRITE_4(sc, ALC_TX_BASE_ADDR_HI, ALC_ADDR_HI(paddr));
+ CSR_WRITE_4(sc, ALC_TDL_HEAD_ADDR_LO, ALC_ADDR_LO(paddr));
+ /* We don't use high priority ring. */
+ CSR_WRITE_4(sc, ALC_TDH_HEAD_ADDR_LO, 0);
+ /* Set Tx descriptor counter. */
+ CSR_WRITE_4(sc, ALC_TD_RING_CNT,
+ (ALC_TX_RING_CNT << TD_RING_CNT_SHIFT) & TD_RING_CNT_MASK);
+ /* Set Rx descriptor base addresses. */
+ paddr = sc->alc_rdata.alc_rx_ring_paddr;
+ CSR_WRITE_4(sc, ALC_RX_BASE_ADDR_HI, ALC_ADDR_HI(paddr));
+ CSR_WRITE_4(sc, ALC_RD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr));
+ /* We use one Rx ring. */
+ CSR_WRITE_4(sc, ALC_RD1_HEAD_ADDR_LO, 0);
+ CSR_WRITE_4(sc, ALC_RD2_HEAD_ADDR_LO, 0);
+ CSR_WRITE_4(sc, ALC_RD3_HEAD_ADDR_LO, 0);
+ /* Set Rx descriptor counter. */
+ CSR_WRITE_4(sc, ALC_RD_RING_CNT,
+ (ALC_RX_RING_CNT << RD_RING_CNT_SHIFT) & RD_RING_CNT_MASK);
+
+ /*
+ * Let hardware split jumbo frames into alc_max_buf_sized chunks.
+ * if it do not fit the buffer size. Rx return descriptor holds
+ * a counter that indicates how many fragments were made by the
+ * hardware. The buffer size should be multiple of 8 bytes.
+ * Since hardware has limit on the size of buffer size, always
+ * use the maximum value.
+ * For strict-alignment architectures make sure to reduce buffer
+ * size by 8 bytes to make room for alignment fixup.
+ */
+ sc->alc_buf_size = RX_BUF_SIZE_MAX;
+ CSR_WRITE_4(sc, ALC_RX_BUF_SIZE, sc->alc_buf_size);
+
+ paddr = sc->alc_rdata.alc_rr_ring_paddr;
+ /* Set Rx return descriptor base addresses. */
+ CSR_WRITE_4(sc, ALC_RRD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr));
+ /* We use one Rx return ring. */
+ CSR_WRITE_4(sc, ALC_RRD1_HEAD_ADDR_LO, 0);
+ CSR_WRITE_4(sc, ALC_RRD2_HEAD_ADDR_LO, 0);
+ CSR_WRITE_4(sc, ALC_RRD3_HEAD_ADDR_LO, 0);
+ /* Set Rx return descriptor counter. */
+ CSR_WRITE_4(sc, ALC_RRD_RING_CNT,
+ (ALC_RR_RING_CNT << RRD_RING_CNT_SHIFT) & RRD_RING_CNT_MASK);
+ paddr = sc->alc_rdata.alc_cmb_paddr;
+ CSR_WRITE_4(sc, ALC_CMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr));
+ paddr = sc->alc_rdata.alc_smb_paddr;
+ CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_HI, ALC_ADDR_HI(paddr));
+ CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr));
+
+ /* Tell hardware that we're ready to load DMA blocks. */
+ CSR_WRITE_4(sc, ALC_DMA_BLOCK, DMA_BLOCK_LOAD);
+
+ /* Configure interrupt moderation timer. */
+ sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT;
+ sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT;
+ reg = ALC_USECS(sc->alc_int_rx_mod) << IM_TIMER_RX_SHIFT;
+ reg |= ALC_USECS(sc->alc_int_tx_mod) << IM_TIMER_TX_SHIFT;
+ CSR_WRITE_4(sc, ALC_IM_TIMER, reg);
+ reg = CSR_READ_4(sc, ALC_MASTER_CFG);
+ reg &= ~(MASTER_CHIP_REV_MASK | MASTER_CHIP_ID_MASK);
+ /*
+ * We don't want to automatic interrupt clear as task queue
+ * for the interrupt should know interrupt status.
+ */
+ reg &= ~MASTER_INTR_RD_CLR;
+ reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB);
+ if (ALC_USECS(sc->alc_int_rx_mod) != 0)
+ reg |= MASTER_IM_RX_TIMER_ENB;
+ if (ALC_USECS(sc->alc_int_tx_mod) != 0)
+ reg |= MASTER_IM_TX_TIMER_ENB;
+ CSR_WRITE_4(sc, ALC_MASTER_CFG, reg);
+ /*
+ * Disable interrupt re-trigger timer. We don't want automatic
+ * re-triggering of un-ACKed interrupts.
+ */
+ CSR_WRITE_4(sc, ALC_INTR_RETRIG_TIMER, ALC_USECS(0));
+ /* Configure CMB. */
+ CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, 4);
+ if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0)
+ CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(5000));
+ else
+ CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(0));
+ /*
+ * Hardware can be configured to issue SMB interrupt based
+ * on programmed interval. Since there is a callout that is
+ * invoked for every hz in driver we use that instead of
+ * relying on periodic SMB interrupt.
+ */
+ CSR_WRITE_4(sc, ALC_SMB_STAT_TIMER, ALC_USECS(0));
+ /* Clear MAC statistics. */
+ alc_stats_clear(sc);
+
+ /*
+ * Always use maximum frame size that controller can support.
+ * Otherwise received frames that has larger frame length
+ * than alc(4) MTU would be silently dropped in hardware. This
+ * would make path-MTU discovery hard as sender wouldn't get
+ * any responses from receiver. alc(4) supports
+ * multi-fragmented frames on Rx path so it has no issue on
+ * assembling fragmented frames. Using maximum frame size also
+ * removes the need to reinitialize hardware when interface
+ * MTU configuration was changed.
+ *
+ * Be conservative in what you do, be liberal in what you
+ * accept from others - RFC 793.
+ */
+ CSR_WRITE_4(sc, ALC_FRAME_SIZE, ALC_JUMBO_FRAMELEN);
+
+ /* Disable header split(?) */
+ CSR_WRITE_4(sc, ALC_HDS_CFG, 0);
+
+ /* Configure IPG/IFG parameters. */
+ CSR_WRITE_4(sc, ALC_IPG_IFG_CFG,
+ ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK) |
+ ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) |
+ ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) |
+ ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK));
+ /* Set parameters for half-duplex media. */
+ CSR_WRITE_4(sc, ALC_HDPX_CFG,
+ ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) &
+ HDPX_CFG_LCOL_MASK) |
+ ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) &
+ HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN |
+ ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) &
+ HDPX_CFG_ABEBT_MASK) |
+ ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) &
+ HDPX_CFG_JAMIPG_MASK));
+ /*
+ * Set TSO/checksum offload threshold. For frames that is
+ * larger than this threshold, hardware wouldn't do
+ * TSO/checksum offloading.
+ */
+ CSR_WRITE_4(sc, ALC_TSO_OFFLOAD_THRESH,
+ (ALC_JUMBO_FRAMELEN >> TSO_OFFLOAD_THRESH_UNIT_SHIFT) &
+ TSO_OFFLOAD_THRESH_MASK);
+ /* Configure TxQ. */
+ reg = (alc_dma_burst[sc->alc_dma_rd_burst] <<
+ TXQ_CFG_TX_FIFO_BURST_SHIFT) & TXQ_CFG_TX_FIFO_BURST_MASK;
+ reg |= (TXQ_CFG_TD_BURST_DEFAULT << TXQ_CFG_TD_BURST_SHIFT) &
+ TXQ_CFG_TD_BURST_MASK;
+ CSR_WRITE_4(sc, ALC_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE);
+
+ /* Configure Rx free descriptor pre-fetching. */
+ CSR_WRITE_4(sc, ALC_RX_RD_FREE_THRESH,
+ ((RX_RD_FREE_THRESH_HI_DEFAULT << RX_RD_FREE_THRESH_HI_SHIFT) &
+ RX_RD_FREE_THRESH_HI_MASK) |
+ ((RX_RD_FREE_THRESH_LO_DEFAULT << RX_RD_FREE_THRESH_LO_SHIFT) &
+ RX_RD_FREE_THRESH_LO_MASK));
+
+ /*
+ * Configure flow control parameters.
+ * XON : 80% of Rx FIFO
+ * XOFF : 30% of Rx FIFO
+ */
+ reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN);
+ rxf_hi = (reg * 8) / 10;
+ rxf_lo = (reg * 3)/ 10;
+ CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH,
+ ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) &
+ RX_FIFO_PAUSE_THRESH_LO_MASK) |
+ ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) &
+ RX_FIFO_PAUSE_THRESH_HI_MASK));
+
+ /* Disable RSS until I understand L1C/L2C's RSS logic. */
+ CSR_WRITE_4(sc, ALC_RSS_IDT_TABLE0, 0);
+ CSR_WRITE_4(sc, ALC_RSS_CPU, 0);
+
+ /* Configure RxQ. */
+ reg = (RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) &
+ RXQ_CFG_RD_BURST_MASK;
+ reg |= RXQ_CFG_RSS_MODE_DIS;
+ if ((sc->alc_flags & ALC_FLAG_ASPM_MON) != 0)
+ reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_100M;
+ CSR_WRITE_4(sc, ALC_RXQ_CFG, reg);
+
+ /* Configure Rx DMAW request thresold. */
+ CSR_WRITE_4(sc, ALC_RD_DMA_CFG,
+ ((RD_DMA_CFG_THRESH_DEFAULT << RD_DMA_CFG_THRESH_SHIFT) &
+ RD_DMA_CFG_THRESH_MASK) |
+ ((ALC_RD_DMA_CFG_USECS(0) << RD_DMA_CFG_TIMER_SHIFT) &
+ RD_DMA_CFG_TIMER_MASK));
+ /* Configure DMA parameters. */
+ reg = DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI;
+ reg |= sc->alc_rcb;
+ if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0)
+ reg |= DMA_CFG_CMB_ENB;
+ if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0)
+ reg |= DMA_CFG_SMB_ENB;
+ else
+ reg |= DMA_CFG_SMB_DIS;
+ reg |= (sc->alc_dma_rd_burst & DMA_CFG_RD_BURST_MASK) <<
+ DMA_CFG_RD_BURST_SHIFT;
+ reg |= (sc->alc_dma_wr_burst & DMA_CFG_WR_BURST_MASK) <<
+ DMA_CFG_WR_BURST_SHIFT;
+ reg |= (DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) &
+ DMA_CFG_RD_DELAY_CNT_MASK;
+ reg |= (DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) &
+ DMA_CFG_WR_DELAY_CNT_MASK;
+ CSR_WRITE_4(sc, ALC_DMA_CFG, reg);
+
+ /*
+ * Configure Tx/Rx MACs.
+ * - Auto-padding for short frames.
+ * - Enable CRC generation.
+ * Actual reconfiguration of MAC for resolved speed/duplex
+ * is followed after detection of link establishment.
+ * AR8131/AR8132 always does checksum computation regardless
+ * of MAC_CFG_RXCSUM_ENB bit. Also the controller is known to
+ * have bug in protocol field in Rx return structure so
+ * these controllers can't handle fragmented frames. Disable
+ * Rx checksum offloading until there is a newer controller
+ * that has sane implementation.
+ */
+ reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX |
+ ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) &
+ MAC_CFG_PREAMBLE_MASK);
+ if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0)
+ reg |= MAC_CFG_SPEED_10_100;
+ else
+ reg |= MAC_CFG_SPEED_1000;
+ CSR_WRITE_4(sc, ALC_MAC_CFG, reg);
+
+ /* Set up the receive filter. */
+ alc_iff(sc);
+ alc_rxvlan(sc);
+
+ /* Acknowledge all pending interrupts and clear it. */
+ CSR_WRITE_4(sc, ALC_INTR_MASK, ALC_INTRS);
+ CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF);
+ CSR_WRITE_4(sc, ALC_INTR_STATUS, 0);
+
+ sc->alc_flags &= ~ALC_FLAG_LINK;
+ /* Switch to the current media. */
+ mii = &sc->sc_miibus;
+ mii_mediachg(mii);
+
+ callout_schedule(&sc->sc_tick_ch, hz);
+
+ ifp->if_flags |= IFF_RUNNING;
+ ifp->if_flags &= ~IFF_OACTIVE;
+
+ return (0);
+}
+
+static void
+alc_stop(struct ifnet *ifp, int disable)
+{
+ struct alc_softc *sc = ifp->if_softc;
+ struct alc_txdesc *txd;
+ struct alc_rxdesc *rxd;
+ uint32_t reg;
+ int i;
+
+ callout_stop(&sc->sc_tick_ch);
+
+ /*
+ * Mark the interface down and cancel the watchdog timer.
+ */
+ ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
+ ifp->if_timer = 0;
+
+ sc->alc_flags &= ~ALC_FLAG_LINK;
+
+ alc_stats_update(sc);
+
+ mii_down(&sc->sc_miibus);
+
+ /* Disable interrupts. */
+ CSR_WRITE_4(sc, ALC_INTR_MASK, 0);
+ CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF);
+ alc_stop_queue(sc);
+
+ /* Disable DMA. */
+ reg = CSR_READ_4(sc, ALC_DMA_CFG);
+ reg &= ~(DMA_CFG_CMB_ENB | DMA_CFG_SMB_ENB);
+ reg |= DMA_CFG_SMB_DIS;
+ CSR_WRITE_4(sc, ALC_DMA_CFG, reg);
+ DELAY(1000);
+
+ /* Stop Rx/Tx MACs. */
+ alc_stop_mac(sc);
+
+ /* Disable interrupts which might be touched in taskq handler. */
+ CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF);
+
+ /* Reclaim Rx buffers that have been processed. */
+ if (sc->alc_cdata.alc_rxhead != NULL)
+ m_freem(sc->alc_cdata.alc_rxhead);
+ ALC_RXCHAIN_RESET(sc);
+ /*
+ * Free Tx/Rx mbufs still in the queues.
+ */
+ for (i = 0; i < ALC_RX_RING_CNT; i++) {
+ rxd = &sc->alc_cdata.alc_rxdesc[i];
+ if (rxd->rx_m != NULL) {
+ bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap);
+ m_freem(rxd->rx_m);
+ rxd->rx_m = NULL;
+ }
+ }
+ for (i = 0; i < ALC_TX_RING_CNT; i++) {
+ txd = &sc->alc_cdata.alc_txdesc[i];
+ if (txd->tx_m != NULL) {
+ bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap);
+ m_freem(txd->tx_m);
+ txd->tx_m = NULL;
+ }
+ }
+}
+
+static void
+alc_stop_mac(struct alc_softc *sc)
+{
+ uint32_t reg;
+ int i;
+
+ /* Disable Rx/Tx MAC. */
+ reg = CSR_READ_4(sc, ALC_MAC_CFG);
+ if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) {
+ reg &= ~MAC_CFG_TX_ENB | MAC_CFG_RX_ENB;
+ CSR_WRITE_4(sc, ALC_MAC_CFG, reg);
+ }
+ for (i = ALC_TIMEOUT; i > 0; i--) {
+ reg = CSR_READ_4(sc, ALC_IDLE_STATUS);
+ if (reg == 0)
+ break;
+ DELAY(10);
+ }
+ if (i == 0)
+ printf("%s: could not disable Rx/Tx MAC(0x%08x)!\n",
+ device_xname(sc->sc_dev), reg);
+}
+
+static void
+alc_start_queue(struct alc_softc *sc)
+{
+ uint32_t qcfg[] = {
+ 0,
+ RXQ_CFG_QUEUE0_ENB,
+ RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB,
+ RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB | RXQ_CFG_QUEUE2_ENB,
+ RXQ_CFG_ENB
+ };
+ uint32_t cfg;
+
+ /* Enable RxQ. */
+ cfg = CSR_READ_4(sc, ALC_RXQ_CFG);
+ cfg &= ~RXQ_CFG_ENB;
+ cfg |= qcfg[1];
+ CSR_WRITE_4(sc, ALC_RXQ_CFG, cfg);
+ /* Enable TxQ. */
+ cfg = CSR_READ_4(sc, ALC_TXQ_CFG);
+ cfg |= TXQ_CFG_ENB;
+ CSR_WRITE_4(sc, ALC_TXQ_CFG, cfg);
+}
+
+static void
+alc_stop_queue(struct alc_softc *sc)
+{
+ uint32_t reg;
+ int i;
+
+ /* Disable RxQ. */
+ reg = CSR_READ_4(sc, ALC_RXQ_CFG);
+ if ((reg & RXQ_CFG_ENB) != 0) {
+ reg &= ~RXQ_CFG_ENB;
+ CSR_WRITE_4(sc, ALC_RXQ_CFG, reg);
+ }
+ /* Disable TxQ. */
+ reg = CSR_READ_4(sc, ALC_TXQ_CFG);
+ if ((reg & TXQ_CFG_ENB) == 0) {
+ reg &= ~TXQ_CFG_ENB;
+ CSR_WRITE_4(sc, ALC_TXQ_CFG, reg);
+ }
+ for (i = ALC_TIMEOUT; i > 0; i--) {
+ reg = CSR_READ_4(sc, ALC_IDLE_STATUS);
+ if ((reg & (IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0)
+ break;
+ DELAY(10);
+ }
+ if (i == 0)
+ printf("%s: could not disable RxQ/TxQ (0x%08x)!\n",
+ device_xname(sc->sc_dev), reg);
+}
+
+static void
+alc_init_tx_ring(struct alc_softc *sc)
+{
+ struct alc_ring_data *rd;
+ struct alc_txdesc *txd;
+ int i;
+
+ sc->alc_cdata.alc_tx_prod = 0;
+ sc->alc_cdata.alc_tx_cons = 0;
+ sc->alc_cdata.alc_tx_cnt = 0;
+
+ rd = &sc->alc_rdata;
+ memset(rd->alc_tx_ring, 0, ALC_TX_RING_SZ);
+ for (i = 0; i < ALC_TX_RING_CNT; i++) {
+ txd = &sc->alc_cdata.alc_txdesc[i];
+ txd->tx_m = NULL;
+ }
+
+ bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 0,
+ sc->alc_cdata.alc_tx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE);
+}
+
+static int
+alc_init_rx_ring(struct alc_softc *sc)
+{
+ struct alc_ring_data *rd;
+ struct alc_rxdesc *rxd;
+ int i;
+
+ sc->alc_cdata.alc_rx_cons = ALC_RX_RING_CNT - 1;
+ rd = &sc->alc_rdata;
+ memset(rd->alc_rx_ring, 0, ALC_RX_RING_SZ);
+ for (i = 0; i < ALC_RX_RING_CNT; i++) {
+ rxd = &sc->alc_cdata.alc_rxdesc[i];
+ rxd->rx_m = NULL;
+ rxd->rx_desc = &rd->alc_rx_ring[i];
+ if (alc_newbuf(sc, rxd, 1) != 0)
+ return (ENOBUFS);
+ }
+
+ /*
+ * Since controller does not update Rx descriptors, driver
+ * does have to read Rx descriptors back so BUS_DMASYNC_PREWRITE
+ * is enough to ensure coherence.
+ */
+ bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map, 0,
+ sc->alc_cdata.alc_rx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE);
+ /* Let controller know availability of new Rx buffers. */
+ CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, sc->alc_cdata.alc_rx_cons);
+
+ return (0);
+}
+
+static void
+alc_init_rr_ring(struct alc_softc *sc)
+{
+ struct alc_ring_data *rd;
+
+ sc->alc_cdata.alc_rr_cons = 0;
+ ALC_RXCHAIN_RESET(sc);
+
+ rd = &sc->alc_rdata;
+ memset(rd->alc_rr_ring, 0, ALC_RR_RING_SZ);
+ bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map, 0,
+ sc->alc_cdata.alc_rr_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE);
+}
+
+static void
+alc_init_cmb(struct alc_softc *sc)
+{
+ struct alc_ring_data *rd;
+
+ rd = &sc->alc_rdata;
+ memset(rd->alc_cmb, 0, ALC_CMB_SZ);
+ bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_cmb_map, 0,
+ sc->alc_cdata.alc_cmb_map->dm_mapsize, BUS_DMASYNC_PREWRITE);
+}
+
+static void
+alc_init_smb(struct alc_softc *sc)
+{
+ struct alc_ring_data *rd;
+
+ rd = &sc->alc_rdata;
+ memset(rd->alc_smb, 0, ALC_SMB_SZ);
+ bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0,
+ sc->alc_cdata.alc_smb_map->dm_mapsize, BUS_DMASYNC_PREWRITE);
+}
+
+static void
+alc_rxvlan(struct alc_softc *sc)
+{
+ struct ifnet *ifp = &sc->sc_ec.ec_if;
+ uint32_t reg;
+
+ reg = CSR_READ_4(sc, ALC_MAC_CFG);
+ if (ifp->if_capabilities & ETHERCAP_VLAN_HWTAGGING)
+ reg |= MAC_CFG_VLAN_TAG_STRIP;
+ else
+ reg &= ~MAC_CFG_VLAN_TAG_STRIP;
+ CSR_WRITE_4(sc, ALC_MAC_CFG, reg);
+}
+
+static void
+alc_iff(struct alc_softc *sc)
+{
+ struct ethercom *ec = &sc->sc_ec;
+ struct ifnet *ifp = &ec->ec_if;
+ struct ether_multi *enm;
+ struct ether_multistep step;
+ uint32_t crc;
+ uint32_t mchash[2];
+ uint32_t rxcfg;
+
+ rxcfg = CSR_READ_4(sc, ALC_MAC_CFG);
+ rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC);
+ ifp->if_flags &= ~IFF_ALLMULTI;
+
+ /*
+ * Always accept broadcast frames.
+ */
+ rxcfg |= MAC_CFG_BCAST;
+
+ if (ifp->if_flags & IFF_PROMISC || ec->ec_multicnt > 0) {
+ ifp->if_flags |= IFF_ALLMULTI;
+ if (ifp->if_flags & IFF_PROMISC)
+ rxcfg |= MAC_CFG_PROMISC;
+ else
+ rxcfg |= MAC_CFG_ALLMULTI;
+ mchash[0] = mchash[1] = 0xFFFFFFFF;
+ } else {
+ /* Program new filter. */
+ memset(mchash, 0, sizeof(mchash));
+
+ ETHER_FIRST_MULTI(step, ec, enm);
+ while (enm != NULL) {
+ crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN);
+ mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f);
+ ETHER_NEXT_MULTI(step, enm);
+ }
+ }
+
+ CSR_WRITE_4(sc, ALC_MAR0, mchash[0]);
+ CSR_WRITE_4(sc, ALC_MAR1, mchash[1]);
+ CSR_WRITE_4(sc, ALC_MAC_CFG, rxcfg);
+}
--- /dev/null 2011-01-21 10:30:24.000000000 +0100
+++ sys/dev/pci/if_alcreg.h 2011-01-16 12:59:36.000000000 +0100
@@ -0,0 +1,1173 @@
+/* $OpenBSD: if_alcreg.h,v 1.1 2009/08/08 09:31:13 kevlo Exp $ */
+/*-
+ * Copyright (c) 2009, Pyun YongHyeon <yongari%FreeBSD.org@localhost>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice unmodified, this list of conditions, and the following
+ * disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMATES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMATE.
+ *
+ * $FreeBSD: src/sys/dev/alc/if_alcreg.h,v 1.1 2009/06/10 02:07:58 yongari Exp
$
+ */
+
+#ifndef _IF_ALCREG_H
+#define _IF_ALCREG_H
+
+#define ALC_PCIR_BAR 0x10
+
+/* 0x0000 - 0x02FF : PCIe configuration space */
+
+#define ALC_PEX_UNC_ERR_SEV 0x10C
+#define PEX_UNC_ERR_SEV_TRN 0x00000001
+#define PEX_UNC_ERR_SEV_DLP 0x00000010
+#define PEX_UNC_ERR_SEV_PSN_TLP 0x00001000
+#define PEX_UNC_ERR_SEV_FCP 0x00002000
+#define PEX_UNC_ERR_SEV_CPL_TO 0x00004000
+#define PEX_UNC_ERR_SEV_CA 0x00008000
+#define PEX_UNC_ERR_SEV_UC 0x00010000
+#define PEX_UNC_ERR_SEV_ROV 0x00020000
+#define PEX_UNC_ERR_SEV_MLFP 0x00040000
+#define PEX_UNC_ERR_SEV_ECRC 0x00080000
+#define PEX_UNC_ERR_SEV_UR 0x00100000
+
+#define ALC_TWSI_CFG 0x218
+#define TWSI_CFG_SW_LD_START 0x00000800
+#define TWSI_CFG_HW_LD_START 0x00001000
+#define TWSI_CFG_LD_EXIST 0x00400000
+
+#define ALC_PCIE_PHYMISC 0x1000
+#define PCIE_PHYMISC_FORCE_RCV_DET 0x00000004
+
+#define ALC_TWSI_DEBUG 0x1108
+#define TWSI_DEBUG_DEV_EXIST 0x20000000
+
+#define ALC_EEPROM_CFG 0x12C0
+#define EEPROM_CFG_DATA_HI_MASK 0x0000FFFF
+#define EEPROM_CFG_ADDR_MASK 0x03FF0000
+#define EEPROM_CFG_ACK 0x40000000
+#define EEPROM_CFG_RW 0x80000000
+#define EEPROM_CFG_DATA_HI_SHIFT 0
+#define EEPROM_CFG_ADDR_SHIFT 16
+
+#define ALC_EEPROM_DATA_LO 0x12C4
+
+#define ALC_OPT_CFG 0x12F0
+#define OPT_CFG_CLK_ENB 0x00000002
+
+#define ALC_PM_CFG 0x12F8
+#define PM_CFG_SERDES_ENB 0x00000001
+#define PM_CFG_RBER_ENB 0x00000002
+#define PM_CFG_CLK_REQ_ENB 0x00000004
+#define PM_CFG_ASPM_L1_ENB 0x00000008
+#define PM_CFG_SERDES_L1_ENB 0x00000010
+#define PM_CFG_SERDES_PLL_L1_ENB 0x00000020
+#define PM_CFG_SERDES_PD_EX_L1 0x00000040
+#define PM_CFG_SERDES_BUDS_RX_L1_ENB 0x00000080
+#define PM_CFG_L0S_ENTRY_TIMER_MASK 0x00000F00
+#define PM_CFG_ASPM_L0S_ENB 0x00001000
+#define PM_CFG_CLK_SWH_L1 0x00002000
+#define PM_CFG_CLK_PWM_VER1_1 0x00004000
+#define PM_CFG_PCIE_RECV 0x00008000
+#define PM_CFG_L1_ENTRY_TIMER_MASK 0x000F0000
+#define PM_CFG_PM_REQ_TIMER_MASK 0x00F00000
+#define PM_CFG_LCKDET_TIMER_MASK 0x3F000000
+#define PM_CFG_MAC_ASPM_CHK 0x40000000
+#define PM_CFG_HOTRST 0x80000000
+#define PM_CFG_L0S_ENTRY_TIMER_SHIFT 8
+#define PM_CFG_L1_ENTRY_TIMER_SHIFT 16
+#define PM_CFG_PM_REQ_TIMER_SHIFT 20
+#define PM_CFG_LCKDET_TIMER_SHIFT 24
+
+#define ALC_MASTER_CFG 0x1400
+#define MASTER_RESET 0x00000001
+#define MASTER_BERT_START 0x00000010
+#define MASTER_TEST_MODE_MASK 0x000000C0
+#define MASTER_MTIMER_ENB 0x00000100
+#define MASTER_MANUAL_INTR_ENB 0x00000200
+#define MASTER_IM_TX_TIMER_ENB 0x00000400
+#define MASTER_IM_RX_TIMER_ENB 0x00000800
+#define MASTER_CLK_SEL_DIS 0x00001000
+#define MASTER_CLK_SWH_MODE 0x00002000
+#define MASTER_INTR_RD_CLR 0x00004000
+#define MASTER_CHIP_REV_MASK 0x00FF0000
+#define MASTER_CHIP_ID_MASK 0x7F000000
+#define MASTER_OTP_SEL 0x80000000
+#define MASTER_TEST_MODE_SHIFT 2
+#define MASTER_CHIP_REV_SHIFT 16
+#define MASTER_CHIP_ID_SHIFT 24
+
+/* Number of ticks per usec for AR8131/AR8132. */
+#define ALC_TICK_USECS 2
+#define ALC_USECS(x) ((x) / ALC_TICK_USECS)
+
+#define ALC_MANUAL_TIMER 0x1404
+
+#define ALC_IM_TIMER 0x1408
+#define IM_TIMER_TX_MASK 0x0000FFFF
+#define IM_TIMER_RX_MASK 0xFFFF0000
+#define IM_TIMER_TX_SHIFT 0
+#define IM_TIMER_RX_SHIFT 16
+#define ALC_IM_TIMER_MIN 0
+#define ALC_IM_TIMER_MAX 130000 /* 130ms */
+/*
+ * 100us will ensure alc(4) wouldn't generate more than 10000 Rx
+ * interrupts in a second.
+ */
+#define ALC_IM_RX_TIMER_DEFAULT 100 /* 100us */
+/*
+ * alc(4) does not rely on Tx completion interrupts, so set it
+ * somewhat large value to reduce Tx completion interrupts.
+ */
+#define ALC_IM_TX_TIMER_DEFAULT 50000 /* 50ms */
+
+#define ALC_GPHY_CFG 0x140C /* 16bits */
+#define GPHY_CFG_EXT_RESET 0x0001
+#define GPHY_CFG_RTL_MODE 0x0002
+#define GPHY_CFG_LED_MODE 0x0004
+#define GPHY_CFG_ANEG_NOW 0x0008
+#define GPHY_CFG_RECV_ANEG 0x0010
+#define GPHY_CFG_GATE_25M_ENB 0x0020
+#define GPHY_CFG_LPW_EXIT 0x0040
+#define GPHY_CFG_PHY_IDDQ 0x0080
+#define GPHY_CFG_PHY_IDDQ_DIS 0x0100
+#define GPHY_CFG_PCLK_SEL_DIS 0x0200
+#define GPHY_CFG_HIB_EN 0x0400
+#define GPHY_CFG_HIB_PULSE 0x0800
+#define GPHY_CFG_SEL_ANA_RESET 0x1000
+#define GPHY_CFG_PHY_PLL_ON 0x2000
+#define GPHY_CFG_PWDOWN_HW 0x4000
+#define GPHY_CFG_PHY_PLL_BYPASS 0x8000
+
+#define ALC_IDLE_STATUS 0x1410
+#define IDLE_STATUS_RXMAC 0x00000001
+#define IDLE_STATUS_TXMAC 0x00000002
+#define IDLE_STATUS_RXQ 0x00000004
+#define IDLE_STATUS_TXQ 0x00000008
+#define IDLE_STATUS_DMARD 0x00000010
+#define IDLE_STATUS_DMAWR 0x00000020
+#define IDLE_STATUS_SMB 0x00000040
+#define IDLE_STATUS_CMB 0x00000080
+
+#define ALC_MDIO 0x1414
+#define MDIO_DATA_MASK 0x0000FFFF
+#define MDIO_REG_ADDR_MASK 0x001F0000
+#define MDIO_OP_READ 0x00200000
+#define MDIO_OP_WRITE 0x00000000
+#define MDIO_SUP_PREAMBLE 0x00400000
+#define MDIO_OP_EXECUTE 0x00800000
+#define MDIO_CLK_25_4 0x00000000
+#define MDIO_CLK_25_6 0x02000000
+#define MDIO_CLK_25_8 0x03000000
+#define MDIO_CLK_25_10 0x04000000
+#define MDIO_CLK_25_14 0x05000000
+#define MDIO_CLK_25_20 0x06000000
+#define MDIO_CLK_25_28 0x07000000
+#define MDIO_OP_BUSY 0x08000000
+#define MDIO_AP_ENB 0x10000000
+#define MDIO_DATA_SHIFT 0
+#define MDIO_REG_ADDR_SHIFT 16
+
+#define MDIO_REG_ADDR(x) \
+ (((x) << MDIO_REG_ADDR_SHIFT) & MDIO_REG_ADDR_MASK)
+/* Default PHY address. */
+#define ALC_PHY_ADDR 0
+
+#define ALC_PHY_STATUS 0x1418
+#define PHY_STATUS_RECV_ENB 0x00000001
+#define PHY_STATUS_GENERAL_MASK 0x0000FFFF
+#define PHY_STATUS_OE_PWSP_MASK 0x07FF0000
+#define PHY_STATUS_LPW_STATE 0x80000000
+#define PHY_STATIS_OE_PWSP_SHIFT 16
+
+/* Packet memory BIST. */
+#define ALC_BIST0 0x141C
+#define BIST0_ENB 0x00000001
+#define BIST0_SRAM_FAIL 0x00000002
+#define BIST0_FUSE_FLAG 0x00000004
+
+/* PCIe retry buffer BIST. */
+#define ALC_BIST1 0x1420
+#define BIST1_ENB 0x00000001
+#define BIST1_SRAM_FAIL 0x00000002
+#define BIST1_FUSE_FLAG 0x00000004
+
+#define ALC_SERDES_LOCK 0x1424
+#define SERDES_LOCK_DET 0x00000001
+#define SERDES_LOCK_DET_ENB 0x00000002
+
+#define ALC_MAC_CFG 0x1480
+#define MAC_CFG_TX_ENB 0x00000001
+#define MAC_CFG_RX_ENB 0x00000002
+#define MAC_CFG_TX_FC 0x00000004
+#define MAC_CFG_RX_FC 0x00000008
+#define MAC_CFG_LOOP 0x00000010
+#define MAC_CFG_FULL_DUPLEX 0x00000020
+#define MAC_CFG_TX_CRC_ENB 0x00000040
+#define MAC_CFG_TX_AUTO_PAD 0x00000080
+#define MAC_CFG_TX_LENCHK 0x00000100
+#define MAC_CFG_RX_JUMBO_ENB 0x00000200
+#define MAC_CFG_PREAMBLE_MASK 0x00003C00
+#define MAC_CFG_VLAN_TAG_STRIP 0x00004000
+#define MAC_CFG_PROMISC 0x00008000
+#define MAC_CFG_TX_PAUSE 0x00010000
+#define MAC_CFG_SCNT 0x00020000
+#define MAC_CFG_SYNC_RST_TX 0x00040000
+#define MAC_CFG_SIM_RST_TX 0x00080000
+#define MAC_CFG_SPEED_MASK 0x00300000
+#define MAC_CFG_SPEED_10_100 0x00100000
+#define MAC_CFG_SPEED_1000 0x00200000
+#define MAC_CFG_DBG_TX_BACKOFF 0x00400000
+#define MAC_CFG_TX_JUMBO_ENB 0x00800000
+#define MAC_CFG_RXCSUM_ENB 0x01000000
+#define MAC_CFG_ALLMULTI 0x02000000
+#define MAC_CFG_BCAST 0x04000000
+#define MAC_CFG_DBG 0x08000000
+#define MAC_CFG_SINGLE_PAUSE_ENB 0x10000000
+#define MAC_CFG_PREAMBLE_SHIFT 10
+#define MAC_CFG_PREAMBLE_DEFAULT 7
+
+#define ALC_IPG_IFG_CFG 0x1484
+#define IPG_IFG_IPGT_MASK 0x0000007F
+#define IPG_IFG_MIFG_MASK 0x0000FF00
+#define IPG_IFG_IPG1_MASK 0x007F0000
+#define IPG_IFG_IPG2_MASK 0x7F000000
+#define IPG_IFG_IPGT_SHIFT 0
+#define IPG_IFG_IPGT_DEFAULT 0x60
+#define IPG_IFG_MIFG_SHIFT 8
+#define IPG_IFG_MIFG_DEFAULT 0x50
+#define IPG_IFG_IPG1_SHIFT 16
+#define IPG_IFG_IPG1_DEFAULT 0x40
+#define IPG_IFG_IPG2_SHIFT 24
+#define IPG_IFG_IPG2_DEFAULT 0x60
+
+/* Station address. */
+#define ALC_PAR0 0x1488
+#define ALC_PAR1 0x148C
+
+/* 64bit multicast hash register. */
+#define ALC_MAR0 0x1490
+#define ALC_MAR1 0x1494
+
+/* half-duplex parameter configuration. */
+#define ALC_HDPX_CFG 0x1498
+#define HDPX_CFG_LCOL_MASK 0x000003FF
+#define HDPX_CFG_RETRY_MASK 0x0000F000
+#define HDPX_CFG_EXC_DEF_EN 0x00010000
+#define HDPX_CFG_NO_BACK_C 0x00020000
+#define HDPX_CFG_NO_BACK_P 0x00040000
+#define HDPX_CFG_ABEBE 0x00080000
+#define HDPX_CFG_ABEBT_MASK 0x00F00000
+#define HDPX_CFG_JAMIPG_MASK 0x0F000000
+#define HDPX_CFG_LCOL_SHIFT 0
+#define HDPX_CFG_LCOL_DEFAULT 0x37
+#define HDPX_CFG_RETRY_SHIFT 12
+#define HDPX_CFG_RETRY_DEFAULT 0x0F
+#define HDPX_CFG_ABEBT_SHIFT 20
+#define HDPX_CFG_ABEBT_DEFAULT 0x0A
+#define HDPX_CFG_JAMIPG_SHIFT 24
+#define HDPX_CFG_JAMIPG_DEFAULT 0x07
+
+#define ALC_FRAME_SIZE 0x149C
+
+#define ALC_WOL_CFG 0x14A0
+#define WOL_CFG_PATTERN 0x00000001
+#define WOL_CFG_PATTERN_ENB 0x00000002
+#define WOL_CFG_MAGIC 0x00000004
+#define WOL_CFG_MAGIC_ENB 0x00000008
+#define WOL_CFG_LINK_CHG 0x00000010
+#define WOL_CFG_LINK_CHG_ENB 0x00000020
+#define WOL_CFG_PATTERN_DET 0x00000100
+#define WOL_CFG_MAGIC_DET 0x00000200
+#define WOL_CFG_LINK_CHG_DET 0x00000400
+#define WOL_CFG_CLK_SWITCH_ENB 0x00008000
+#define WOL_CFG_PATTERN0 0x00010000
+#define WOL_CFG_PATTERN1 0x00020000
+#define WOL_CFG_PATTERN2 0x00040000
+#define WOL_CFG_PATTERN3 0x00080000
+#define WOL_CFG_PATTERN4 0x00100000
+#define WOL_CFG_PATTERN5 0x00200000
+#define WOL_CFG_PATTERN6 0x00400000
+
+/* WOL pattern length. */
+#define ALC_PATTERN_CFG0 0x14A4
+#define PATTERN_CFG_0_LEN_MASK 0x0000007F
+#define PATTERN_CFG_1_LEN_MASK 0x00007F00
+#define PATTERN_CFG_2_LEN_MASK 0x007F0000
+#define PATTERN_CFG_3_LEN_MASK 0x7F000000
+
+#define ALC_PATTERN_CFG1 0x14A8
+#define PATTERN_CFG_4_LEN_MASK 0x0000007F
+#define PATTERN_CFG_5_LEN_MASK 0x00007F00
+#define PATTERN_CFG_6_LEN_MASK 0x007F0000
+
+/* RSS */
+#define ALC_RSS_KEY0 0x14B0
+
+#define ALC_RSS_KEY1 0x14B4
+
+#define ALC_RSS_KEY2 0x14B8
+
+#define ALC_RSS_KEY3 0x14BC
+
+#define ALC_RSS_KEY4 0x14C0
+
+#define ALC_RSS_KEY5 0x14C4
+
+#define ALC_RSS_KEY6 0x14C8
+
+#define ALC_RSS_KEY7 0x14CC
+
+#define ALC_RSS_KEY8 0x14D0
+
+#define ALC_RSS_KEY9 0x14D4
+
+#define ALC_RSS_IDT_TABLE0 0x14E0
+
+#define ALC_RSS_IDT_TABLE1 0x14E4
+
+#define ALC_RSS_IDT_TABLE2 0x14E8
+
+#define ALC_RSS_IDT_TABLE3 0x14EC
+
+#define ALC_RSS_IDT_TABLE4 0x14F0
+
+#define ALC_RSS_IDT_TABLE5 0x14F4
+
+#define ALC_RSS_IDT_TABLE6 0x14F8
+
+#define ALC_RSS_IDT_TABLE7 0x14FC
+
+#define ALC_SRAM_RD0_ADDR 0x1500
+
+#define ALC_SRAM_RD1_ADDR 0x1504
+
+#define ALC_SRAM_RD2_ADDR 0x1508
+
+#define ALC_SRAM_RD3_ADDR 0x150C
+
+#define RD_HEAD_ADDR_MASK 0x000003FF
+#define RD_TAIL_ADDR_MASK 0x03FF0000
+#define RD_HEAD_ADDR_SHIFT 0
+#define RD_TAIL_ADDR_SHIFT 16
+
+#define ALC_RD_NIC_LEN0 0x1510 /* 8 bytes unit */
+#define RD_NIC_LEN_MASK 0x000003FF
+
+#define ALC_RD_NIC_LEN1 0x1514
+
+#define ALC_SRAM_TD_ADDR 0x1518
+#define TD_HEAD_ADDR_MASK 0x000003FF
+#define TD_TAIL_ADDR_MASK 0x03FF0000
+#define TD_HEAD_ADDR_SHIFT 0
+#define TD_TAIL_ADDR_SHIFT 16
+
+#define ALC_SRAM_TD_LEN 0x151C /* 8 bytes unit */
+#define SRAM_TD_LEN_MASK 0x000003FF
+
+#define ALC_SRAM_RX_FIFO_ADDR 0x1520
+
+#define ALC_SRAM_RX_FIFO_LEN 0x1524
+
+#define ALC_SRAM_TX_FIFO_ADDR 0x1528
+
+#define ALC_SRAM_TX_FIFO_LEN 0x152C
+
+#define ALC_SRAM_TCPH_ADDR 0x1530
+#define SRAM_TCPH_ADDR_MASK 0x00000FFF
+#define SRAM_PATH_ADDR_MASK 0x0FFF0000
+#define SRAM_TCPH_ADDR_SHIFT 0
+#define SRAM_PKTH_ADDR_SHIFT 16
+
+#define ALC_DMA_BLOCK 0x1534
+#define DMA_BLOCK_LOAD 0x00000001
+
+#define ALC_RX_BASE_ADDR_HI 0x1540
+
+#define ALC_TX_BASE_ADDR_HI 0x1544
+
+#define ALC_SMB_BASE_ADDR_HI 0x1548
+
+#define ALC_SMB_BASE_ADDR_LO 0x154C
+
+#define ALC_RD0_HEAD_ADDR_LO 0x1550
+
+#define ALC_RD1_HEAD_ADDR_LO 0x1554
+
+#define ALC_RD2_HEAD_ADDR_LO 0x1558
+
+#define ALC_RD3_HEAD_ADDR_LO 0x155C
+
+#define ALC_RD_RING_CNT 0x1560
+#define RD_RING_CNT_MASK 0x00000FFF
+#define RD_RING_CNT_SHIFT 0
+
+#define ALC_RX_BUF_SIZE 0x1564
+#define RX_BUF_SIZE_MASK 0x0000FFFF
+/*
+ * If larger buffer size than 1536 is specified the controller
+ * will be locked up. This is hardware limitation.
+ */
+#define RX_BUF_SIZE_MAX 1536
+
+#define ALC_RRD0_HEAD_ADDR_LO 0x1568
+
+#define ALC_RRD1_HEAD_ADDR_LO 0x156C
+
+#define ALC_RRD2_HEAD_ADDR_LO 0x1570
+
+#define ALC_RRD3_HEAD_ADDR_LO 0x1574
+
+#define ALC_RRD_RING_CNT 0x1578
+#define RRD_RING_CNT_MASK 0x00000FFF
+#define RRD_RING_CNT_SHIFT 0
+
+#define ALC_TDH_HEAD_ADDR_LO 0x157C
+
+#define ALC_TDL_HEAD_ADDR_LO 0x1580
+
+#define ALC_TD_RING_CNT 0x1584
+#define TD_RING_CNT_MASK 0x0000FFFF
+#define TD_RING_CNT_SHIFT 0
+
+#define ALC_CMB_BASE_ADDR_LO 0x1588
+
+#define ALC_TXQ_CFG 0x1590
+#define TXQ_CFG_TD_BURST_MASK 0x0000000F
+#define TXQ_CFG_IP_OPTION_ENB 0x00000010
+#define TXQ_CFG_ENB 0x00000020
+#define TXQ_CFG_ENHANCED_MODE 0x00000040
+#define TXQ_CFG_8023_ENB 0x00000080
+#define TXQ_CFG_TX_FIFO_BURST_MASK 0xFFFF0000
+#define TXQ_CFG_TD_BURST_SHIFT 0
+#define TXQ_CFG_TD_BURST_DEFAULT 5
+#define TXQ_CFG_TX_FIFO_BURST_SHIFT 16
+
+#define ALC_TSO_OFFLOAD_THRESH 0x1594 /* 8 bytes unit */
+#define TSO_OFFLOAD_THRESH_MASK 0x000007FF
+#define TSO_OFFLOAD_THRESH_SHIFT 0
+#define TSO_OFFLOAD_THRESH_UNIT 8
+#define TSO_OFFLOAD_THRESH_UNIT_SHIFT 3
+
+#define ALC_TXF_WATER_MARK 0x1598 /* 8 bytes unit */
+#define TXF_WATER_MARK_HI_MASK 0x00000FFF
+#define TXF_WATER_MARK_LO_MASK 0x0FFF0000
+#define TXF_WATER_MARK_BURST_ENB 0x80000000
+#define TXF_WATER_MARK_LO_SHIFT 0
+#define TXF_WATER_MARK_HI_SHIFT 16
+
+#define ALC_THROUGHPUT_MON 0x159C
+#define THROUGHPUT_MON_RATE_MASK 0x00000003
+#define THROUGHPUT_MON_ENB 0x00000080
+#define THROUGHPUT_MON_RATE_SHIFT 0
+
+#define ALC_RXQ_CFG 0x15A0
+#define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_MASK 0x00000003
+#define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_NONE 0x00000000
+#define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_1M 0x00000001
+#define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_10M 0x00000002
+#define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_100M 0x00000003
+#define RXQ_CFG_QUEUE1_ENB 0x00000010
+#define RXQ_CFG_QUEUE2_ENB 0x00000020
+#define RXQ_CFG_QUEUE3_ENB 0x00000040
+#define RXQ_CFG_IPV6_CSUM_ENB 0x00000080
+#define RXQ_CFG_RSS_HASH_TBL_LEN_MASK 0x0000FF00
+#define RXQ_CFG_RSS_HASH_IPV4 0x00010000
+#define RXQ_CFG_RSS_HASH_IPV4_TCP 0x00020000
+#define RXQ_CFG_RSS_HASH_IPV6 0x00040000
+#define RXQ_CFG_RSS_HASH_IPV6_TCP 0x00080000
+#define RXQ_CFG_RD_BURST_MASK 0x03F00000
+#define RXQ_CFG_RSS_MODE_DIS 0x00000000
+#define RXQ_CFG_RSS_MODE_SQSINT 0x04000000
+#define RXQ_CFG_RSS_MODE_MQUESINT 0x08000000
+#define RXQ_CFG_RSS_MODE_MQUEMINT 0x0C000000
+#define RXQ_CFG_NIP_QUEUE_SEL_TBL 0x10000000
+#define RXQ_CFG_RSS_HASH_ENB 0x20000000
+#define RXQ_CFG_CUT_THROUGH_ENB 0x40000000
+#define RXQ_CFG_QUEUE0_ENB 0x80000000
+#define RXQ_CFG_RSS_HASH_TBL_LEN_SHIFT 8
+#define RXQ_CFG_RD_BURST_DEFAULT 8
+#define RXQ_CFG_RD_BURST_SHIFT 20
+#define RXQ_CFG_ENB \
+ (RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB | \
+ RXQ_CFG_QUEUE2_ENB | RXQ_CFG_QUEUE3_ENB)
+
+#define ALC_RX_RD_FREE_THRESH 0x15A4 /* 8 bytes unit. */
+#define RX_RD_FREE_THRESH_HI_MASK 0x0000003F
+#define RX_RD_FREE_THRESH_LO_MASK 0x00000FC0
+#define RX_RD_FREE_THRESH_HI_SHIFT 0
+#define RX_RD_FREE_THRESH_LO_SHIFT 6
+#define RX_RD_FREE_THRESH_HI_DEFAULT 16
+#define RX_RD_FREE_THRESH_LO_DEFAULT 8
+
+#define ALC_RX_FIFO_PAUSE_THRESH 0x15A8
+#define RX_FIFO_PAUSE_THRESH_LO_MASK 0x00000FFF
+#define RX_FIFO_PAUSE_THRESH_HI_MASK 0x0FFF0000
+#define RX_FIFO_PAUSE_THRESH_LO_SHIFT 0
+#define RX_FIFO_PAUSE_THRESH_HI_SHIFT 16
+
+#define ALC_RD_DMA_CFG 0x15AC
+#define RD_DMA_CFG_THRESH_MASK 0x00000FFF /* 8 bytes unit
*/
+#define RD_DMA_CFG_TIMER_MASK 0xFFFF0000
+#define RD_DMA_CFG_THRESH_SHIFT 0
+#define RD_DMA_CFG_TIMER_SHIFT 16
+#define RD_DMA_CFG_THRESH_DEFAULT 0x100
+#define RD_DMA_CFG_TIMER_DEFAULT 0
+#define RD_DMA_CFG_TICK_USECS 8
+#define ALC_RD_DMA_CFG_USECS(x) ((x) / RD_DMA_CFG_TICK_USECS)
+
+#define ALC_RSS_HASH_VALUE 0x15B0
+
+#define ALC_RSS_HASH_FLAG 0x15B4
+
+#define ALC_RSS_CPU 0x15B8
+
+#define ALC_DMA_CFG 0x15C0
+#define DMA_CFG_IN_ORDER 0x00000001
+#define DMA_CFG_ENH_ORDER 0x00000002
+#define DMA_CFG_OUT_ORDER 0x00000004
+#define DMA_CFG_RCB_64 0x00000000
+#define DMA_CFG_RCB_128 0x00000008
+#define DMA_CFG_RD_BURST_128 0x00000000
+#define DMA_CFG_RD_BURST_256 0x00000010
+#define DMA_CFG_RD_BURST_512 0x00000020
+#define DMA_CFG_RD_BURST_1024 0x00000030
+#define DMA_CFG_RD_BURST_2048 0x00000040
+#define DMA_CFG_RD_BURST_4096 0x00000050
+#define DMA_CFG_WR_BURST_128 0x00000000
+#define DMA_CFG_WR_BURST_256 0x00000080
+#define DMA_CFG_WR_BURST_512 0x00000100
+#define DMA_CFG_WR_BURST_1024 0x00000180
+#define DMA_CFG_WR_BURST_2048 0x00000200
+#define DMA_CFG_WR_BURST_4096 0x00000280
+#define DMA_CFG_RD_REQ_PRI 0x00000400
+#define DMA_CFG_RD_DELAY_CNT_MASK 0x0000F800
+#define DMA_CFG_WR_DELAY_CNT_MASK 0x000F0000
+#define DMA_CFG_CMB_ENB 0x00100000
+#define DMA_CFG_SMB_ENB 0x00200000
+#define DMA_CFG_CMB_NOW 0x00400000
+#define DMA_CFG_SMB_DIS 0x01000000
+#define DMA_CFG_SMB_NOW 0x80000000
+#define DMA_CFG_RD_BURST_MASK 0x07
+#define DMA_CFG_RD_BURST_SHIFT 4
+#define DMA_CFG_WR_BURST_MASK 0x07
+#define DMA_CFG_WR_BURST_SHIFT 7
+#define DMA_CFG_RD_DELAY_CNT_SHIFT 11
+#define DMA_CFG_WR_DELAY_CNT_SHIFT 16
+#define DMA_CFG_RD_DELAY_CNT_DEFAULT 15
+#define DMA_CFG_WR_DELAY_CNT_DEFAULT 4
+
+#define ALC_SMB_STAT_TIMER 0x15C4
+#define SMB_STAT_TIMER_MASK 0x00FFFFFF
+#define SMB_STAT_TIMER_SHIFT 0
+
+#define ALC_CMB_TD_THRESH 0x15C8
+#define CMB_TD_THRESH_MASK 0x0000FFFF
+#define CMB_TD_THRESH_SHIFT 0
+
+#define ALC_CMB_TX_TIMER 0x15CC
+#define CMB_TX_TIMER_MASK 0x0000FFFF
+#define CMB_TX_TIMER_SHIFT 0
+
+#define ALC_MBOX_RD0_PROD_IDX 0x15E0
+
+#define ALC_MBOX_RD1_PROD_IDX 0x15E4
+
+#define ALC_MBOX_RD2_PROD_IDX 0x15E8
+
+#define ALC_MBOX_RD3_PROD_IDX 0x15EC
+
+#define ALC_MBOX_RD_PROD_MASK 0x0000FFFF
+#define MBOX_RD_PROD_SHIFT 0
+
+#define ALC_MBOX_TD_PROD_IDX 0x15F0
+#define MBOX_TD_PROD_HI_IDX_MASK 0x0000FFFF
+#define MBOX_TD_PROD_LO_IDX_MASK 0xFFFF0000
+#define MBOX_TD_PROD_HI_IDX_SHIFT 0
+#define MBOX_TD_PROD_LO_IDX_SHIFT 16
+
+#define ALC_MBOX_TD_CONS_IDX 0x15F4
+#define MBOX_TD_CONS_HI_IDX_MASK 0x0000FFFF
+#define MBOX_TD_CONS_LO_IDX_MASK 0xFFFF0000
+#define MBOX_TD_CONS_HI_IDX_SHIFT 0
+#define MBOX_TD_CONS_LO_IDX_SHIFT 16
+
+#define ALC_MBOX_RD01_CONS_IDX 0x15F8
+#define MBOX_RD0_CONS_IDX_MASK 0x0000FFFF
+#define MBOX_RD1_CONS_IDX_MASK 0xFFFF0000
+#define MBOX_RD0_CONS_IDX_SHIFT 0
+#define MBOX_RD1_CONS_IDX_SHIFT 16
+
+#define ALC_MBOX_RD23_CONS_IDX 0x15FC
+#define MBOX_RD2_CONS_IDX_MASK 0x0000FFFF
+#define MBOX_RD3_CONS_IDX_MASK 0xFFFF0000
+#define MBOX_RD2_CONS_IDX_SHIFT 0
+#define MBOX_RD3_CONS_IDX_SHIFT 16
+
+#define ALC_INTR_STATUS 0x1600
+#define INTR_SMB 0x00000001
+#define INTR_TIMER 0x00000002
+#define INTR_MANUAL_TIMER 0x00000004
+#define INTR_RX_FIFO_OFLOW 0x00000008
+#define INTR_RD0_UNDERRUN 0x00000010
+#define INTR_RD1_UNDERRUN 0x00000020
+#define INTR_RD2_UNDERRUN 0x00000040
+#define INTR_RD3_UNDERRUN 0x00000080
+#define INTR_TX_FIFO_UNDERRUN 0x00000100
+#define INTR_DMA_RD_TO_RST 0x00000200
+#define INTR_DMA_WR_TO_RST 0x00000400
+#define INTR_TX_CREDIT 0x00000800
+#define INTR_GPHY 0x00001000
+#define INTR_GPHY_LOW_PW 0x00002000
+#define INTR_TXQ_TO_RST 0x00004000
+#define INTR_TX_PKT 0x00008000
+#define INTR_RX_PKT0 0x00010000
+#define INTR_RX_PKT1 0x00020000
+#define INTR_RX_PKT2 0x00040000
+#define INTR_RX_PKT3 0x00080000
+#define INTR_MAC_RX 0x00100000
+#define INTR_MAC_TX 0x00200000
+#define INTR_UNDERRUN 0x00400000
+#define INTR_FRAME_ERROR 0x00800000
+#define INTR_FRAME_OK 0x01000000
+#define INTR_CSUM_ERROR 0x02000000
+#define INTR_PHY_LINK_DOWN 0x04000000
+#define INTR_DIS_INT 0x80000000
+
+/* Interrupt Mask Register */
+#define ALC_INTR_MASK 0x1604
+
+#ifdef notyet
+#define INTR_RX_PKT \
+ (INTR_RX_PKT0 | INTR_RX_PKT1 | INTR_RX_PKT2 | \
+ INTR_RX_PKT3)
+#define INTR_RD_UNDERRUN \
+ (INTR_RD0_UNDERRUN | INTR_RD1_UNDERRUN | \
+ INTR_RD2_UNDERRUN | INTR_RD3_UNDERRUN)
+#else
+#define INTR_RX_PKT INTR_RX_PKT0
+#define INTR_RD_UNDERRUN INTR_RD0_UNDERRUN
+#endif
+
+#define ALC_INTRS \
+ (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST | \
+ INTR_TXQ_TO_RST | INTR_RX_PKT | INTR_TX_PKT | \
+ INTR_RX_FIFO_OFLOW | INTR_RD_UNDERRUN | \
+ INTR_TX_FIFO_UNDERRUN)
+
+#define ALC_INTR_RETRIG_TIMER 0x1608
+#define INTR_RETRIG_TIMER_MASK 0x0000FFFF
+#define INTR_RETRIG_TIMER_SHIFT 0
+
+#define ALC_HDS_CFG 0x160C
+#define HDS_CFG_ENB 0x00000001
+#define HDS_CFG_BACKFILLSIZE_MASK 0x000FFF00
+#define HDS_CFG_MAX_HDRSIZE_MASK 0xFFF00000
+#define HDS_CFG_BACKFILLSIZE_SHIFT 8
+#define HDS_CFG_MAX_HDRSIZE_SHIFT 20
+
+/* AR8131/AR8132 registers for MAC statistics */
+#define ALC_RX_MIB_BASE 0x1700
+
+#define ALC_TX_MIB_BASE 0x1760
+
+#define ALC_DEBUG_DATA0 0x1900
+
+#define ALC_DEBUG_DATA1 0x1904
+
+#define ALC_MII_DBG_ADDR 0x1D
+#define ALC_MII_DBG_DATA 0x1E
+
+#define MII_ANA_CFG0 0x00
+#define ANA_RESTART_CAL 0x0001
+#define ANA_MANUL_SWICH_ON_MASK 0x001E
+#define ANA_MAN_ENABLE 0x0020
+#define ANA_SEL_HSP 0x0040
+#define ANA_EN_HB 0x0080
+#define ANA_EN_HBIAS 0x0100
+#define ANA_OEN_125M 0x0200
+#define ANA_EN_LCKDT 0x0400
+#define ANA_LCKDT_PHY 0x0800
+#define ANA_AFE_MODE 0x1000
+#define ANA_VCO_SLOW 0x2000
+#define ANA_VCO_FAST 0x4000
+#define ANA_SEL_CLK125M_DSP 0x8000
+#define ANA_MANUL_SWICH_ON_SHIFT 1
+
+#define MII_ANA_CFG4 0x04
+#define ANA_IECHO_ADJ_MASK 0x0F
+#define ANA_IECHO_ADJ_3_MASK 0x000F
+#define ANA_IECHO_ADJ_2_MASK 0x00F0
+#define ANA_IECHO_ADJ_1_MASK 0x0F00
+#define ANA_IECHO_ADJ_0_MASK 0xF000
+#define ANA_IECHO_ADJ_3_SHIFT 0
+#define ANA_IECHO_ADJ_2_SHIFT 4
+#define ANA_IECHO_ADJ_1_SHIFT 8
+#define ANA_IECHO_ADJ_0_SHIFT 12
+
+#define MII_ANA_CFG5 0x05
+#define ANA_SERDES_CDR_BW_MASK 0x0003
+#define ANA_MS_PAD_DBG 0x0004
+#define ANA_SPEEDUP_DBG 0x0008
+#define ANA_SERDES_TH_LOS_MASK 0x0030
+#define ANA_SERDES_EN_DEEM 0x0040
+#define ANA_SERDES_TXELECIDLE 0x0080
+#define ANA_SERDES_BEACON 0x0100
+#define ANA_SERDES_HALFTXDR 0x0200
+#define ANA_SERDES_SEL_HSP 0x0400
+#define ANA_SERDES_EN_PLL 0x0800
+#define ANA_SERDES_EN 0x1000
+#define ANA_SERDES_EN_LCKDT 0x2000
+#define ANA_SERDES_CDR_BW_SHIFT 0
+#define ANA_SERDES_TH_LOS_SHIFT 4
+
+#define MII_ANA_CFG11 0x0B
+#define ANA_PS_HIB_EN 0x8000
+
+#define MII_ANA_CFG18 0x12
+#define ANA_TEST_MODE_10BT_01MASK 0x0003
+#define ANA_LOOP_SEL_10BT 0x0004
+#define ANA_RGMII_MODE_SW 0x0008
+#define ANA_EN_LONGECABLE 0x0010
+#define ANA_TEST_MODE_10BT_2 0x0020
+#define ANA_EN_10BT_IDLE 0x0400
+#define ANA_EN_MASK_TB 0x0800
+#define ANA_TRIGGER_SEL_TIMER_MASK 0x3000
+#define ANA_INTERVAL_SEL_TIMER_MASK 0xC000
+#define ANA_TEST_MODE_10BT_01SHIFT 0
+#define ANA_TRIGGER_SEL_TIMER_SHIFT 12
+#define ANA_INTERVAL_SEL_TIMER_SHIFT 14
+
+#define MII_ANA_CFG41 0x29
+#define ANA_TOP_PS_EN 0x8000
+
+#define MII_ANA_CFG54 0x36
+#define ANA_LONG_CABLE_TH_100_MASK 0x003F
+#define ANA_DESERVED 0x0040
+#define ANA_EN_LIT_CH 0x0080
+#define ANA_SHORT_CABLE_TH_100_MASK 0x3F00
+#define ANA_BP_BAD_LINK_ACCUM 0x4000
+#define ANA_BP_SMALL_BW 0x8000
+#define ANA_LONG_CABLE_TH_100_SHIFT 0
+#define ANA_SHORT_CABLE_TH_100_SHIFT 8
+
+/* Statistics counters collected by the MAC. */
+struct smb {
+ /* Rx stats. */
+ uint32_t rx_frames;
+ uint32_t rx_bcast_frames;
+ uint32_t rx_mcast_frames;
+ uint32_t rx_pause_frames;
+ uint32_t rx_control_frames;
+ uint32_t rx_crcerrs;
+ uint32_t rx_lenerrs;
+ uint32_t rx_bytes;
+ uint32_t rx_runts;
+ uint32_t rx_fragments;
+ uint32_t rx_pkts_64;
+ uint32_t rx_pkts_65_127;
+ uint32_t rx_pkts_128_255;
+ uint32_t rx_pkts_256_511;
+ uint32_t rx_pkts_512_1023;
+ uint32_t rx_pkts_1024_1518;
+ uint32_t rx_pkts_1519_max;
+ uint32_t rx_pkts_truncated;
+ uint32_t rx_fifo_oflows;
+ uint32_t rx_rrs_errs;
+ uint32_t rx_alignerrs;
+ uint32_t rx_bcast_bytes;
+ uint32_t rx_mcast_bytes;
+ uint32_t rx_pkts_filtered;
+ /* Tx stats. */
+ uint32_t tx_frames;
+ uint32_t tx_bcast_frames;
+ uint32_t tx_mcast_frames;
+ uint32_t tx_pause_frames;
+ uint32_t tx_excess_defer;
+ uint32_t tx_control_frames;
+ uint32_t tx_deferred;
+ uint32_t tx_bytes;
+ uint32_t tx_pkts_64;
+ uint32_t tx_pkts_65_127;
+ uint32_t tx_pkts_128_255;
+ uint32_t tx_pkts_256_511;
+ uint32_t tx_pkts_512_1023;
+ uint32_t tx_pkts_1024_1518;
+ uint32_t tx_pkts_1519_max;
+ uint32_t tx_single_colls;
+ uint32_t tx_multi_colls;
+ uint32_t tx_late_colls;
+ uint32_t tx_excess_colls;
+ uint32_t tx_abort;
+ uint32_t tx_underrun;
+ uint32_t tx_desc_underrun;
+ uint32_t tx_lenerrs;
+ uint32_t tx_pkts_truncated;
+ uint32_t tx_bcast_bytes;
+ uint32_t tx_mcast_bytes;
+ uint32_t updated;
+};
+
+/* CMB(Coalesing message block) */
+struct cmb {
+ uint32_t cons;
+};
+
+/* Rx free descriptor */
+struct rx_desc {
+ uint64_t addr;
+};
+
+/* Rx return descriptor */
+struct rx_rdesc {
+ uint32_t rdinfo;
+#define RRD_CSUM_MASK 0x0000FFFF
+#define RRD_RD_CNT_MASK 0x000F0000
+#define RRD_RD_IDX_MASK 0xFFF00000
+#define RRD_CSUM_SHIFT 0
+#define RRD_RD_CNT_SHIFT 16
+#define RRD_RD_IDX_SHIFT 20
+#define RRD_CSUM(x) \
+ (((x) & RRD_CSUM_MASK) >> RRD_CSUM_SHIFT)
+#define RRD_RD_CNT(x) \
+ (((x) & RRD_RD_CNT_MASK) >> RRD_RD_CNT_SHIFT)
+#define RRD_RD_IDX(x) \
+ (((x) & RRD_RD_IDX_MASK) >> RRD_RD_IDX_SHIFT)
+ uint32_t rss;
+ uint32_t vtag;
+#define RRD_VLAN_MASK 0x0000FFFF
+#define RRD_HEAD_LEN_MASK 0x00FF0000
+#define RRD_HDS_MASK 0x03000000
+#define RRD_HDS_NONE 0x00000000
+#define RRD_HDS_HEAD 0x01000000
+#define RRD_HDS_DATA 0x02000000
+#define RRD_CPU_MASK 0x0C000000
+#define RRD_HASH_FLAG_MASK 0xF0000000
+#define RRD_VLAN_SHIFT 0
+#define RRD_HEAD_LEN_SHIFT 16
+#define RRD_HDS_SHIFT 24
+#define RRD_CPU_SHIFT 26
+#define RRD_HASH_FLAG_SHIFT 28
+#define RRD_VLAN(x) \
+ (((x) & RRD_VLAN_MASK) >> RRD_VLAN_SHIFT)
+#define RRD_HEAD_LEN(x) \
+ (((x) & RRD_HEAD_LEN_MASK) >> RRD_HEAD_LEN_SHIFT)
+#define RRD_CPU(x) \
+ (((x) & RRD_CPU_MASK) >> RRD_CPU_SHIFT)
+ uint32_t status;
+#define RRD_LEN_MASK 0x00003FFF
+#define RRD_LEN_SHIFT 0
+#define RRD_TCP_UDPCSUM_NOK 0x00004000
+#define RRD_IPCSUM_NOK 0x00008000
+#define RRD_VLAN_TAG 0x00010000
+#define RRD_PROTO_MASK 0x000E0000
+#define RRD_PROTO_IPV4 0x00020000
+#define RRD_PROTO_IPV6 0x000C0000
+#define RRD_ERR_SUM 0x00100000
+#define RRD_ERR_CRC 0x00200000
+#define RRD_ERR_ALIGN 0x00400000
+#define RRD_ERR_TRUNC 0x00800000
+#define RRD_ERR_RUNT 0x01000000
+#define RRD_ERR_ICMP 0x02000000
+#define RRD_BCAST 0x04000000
+#define RRD_MCAST 0x08000000
+#define RRD_SNAP_LLC 0x10000000
+#define RRD_ETHER 0x00000000
+#define RRD_FIFO_FULL 0x20000000
+#define RRD_ERR_LENGTH 0x40000000
+#define RRD_VALID 0x80000000
+#define RRD_BYTES(x) \
+ (((x) & RRD_LEN_MASK) >> RRD_LEN_SHIFT)
+#define RRD_IPV4(x) \
+ (((x) & RRD_PROTO_MASK) == RRD_PROTO_IPV4)
+};
+
+/* Tx descriptor */
+struct tx_desc {
+ uint32_t len;
+#define TD_BUFLEN_MASK 0x00003FFF
+#define TD_VLAN_MASK 0xFFFF0000
+#define TD_BUFLEN_SHIFT 0
+#define TX_BYTES(x) \
+ (((x) << TD_BUFLEN_SHIFT) & TD_BUFLEN_MASK)
+#define TD_VLAN_SHIFT 16
+ uint32_t flags;
+#define TD_L4HDR_OFFSET_MASK 0x000000FF /* byte unit */
+#define TD_TCPHDR_OFFSET_MASK 0x000000FF /* byte unit */
+#define TD_PLOAD_OFFSET_MASK 0x000000FF /* 2 bytes unit
*/
+#define TD_CUSTOM_CSUM 0x00000100
+#define TD_IPCSUM 0x00000200
+#define TD_TCPCSUM 0x00000400
+#define TD_UDPCSUM 0x00000800
+#define TD_TSO 0x00001000
+#define TD_TSO_DESCV1 0x00000000
+#define TD_TSO_DESCV2 0x00002000
+#define TD_CON_VLAN_TAG 0x00004000
+#define TD_INS_VLAN_TAG 0x00008000
+#define TD_IPV4_DESCV2 0x00010000
+#define TD_LLC_SNAP 0x00020000
+#define TD_ETHERNET 0x00000000
+#define TD_CUSTOM_CSUM_OFFSET_MASK 0x03FC0000 /* 2 bytes unit
*/
+#define TD_CUSTOM_CSUM_EVEN_PAD 0x40000000
+#define TD_MSS_MASK 0x7FFC0000
+#define TD_EOP 0x80000000
+#define TD_L4HDR_OFFSET_SHIFT 0
+#define TD_TCPHDR_OFFSET_SHIFT 0
+#define TD_PLOAD_OFFSET_SHIFT 0
+#define TD_CUSTOM_CSUM_OFFSET_SHIFT 18
+#define TD_MSS_SHIFT 18
+ uint64_t addr;
+};
+
+#define ALC_TX_RING_CNT 256
+#define ALC_TX_RING_ALIGN sizeof(struct tx_desc)
+#define ALC_RX_RING_CNT 256
+#define ALC_RX_RING_ALIGN sizeof(struct rx_desc)
+#define ALC_RX_BUF_ALIGN 4
+#define ALC_RR_RING_CNT ALC_RX_RING_CNT
+#define ALC_RR_RING_ALIGN sizeof(struct rx_rdesc)
+#define ALC_CMB_ALIGN 8
+#define ALC_SMB_ALIGN 8
+
+#define ALC_TSO_MAXSEGSIZE 4096
+#define ALC_TSO_MAXSIZE (65535 + sizeof(struct
ether_vlan_header))
+#define ALC_MAXTXSEGS 32
+
+#define ALC_ADDR_LO(x) ((uint64_t) (x) & 0xFFFFFFFF)
+#define ALC_ADDR_HI(x) ((uint64_t) (x) >> 32)
+
+#define ALC_DESC_INC(x, y) ((x) = ((x) + 1) % (y))
+
+/* Water mark to kick reclaiming Tx buffers. */
+#define ALC_TX_DESC_HIWAT ((ALC_TX_RING_CNT * 6) / 10)
+
+#define ALC_MSI_MESSAGES 1
+#define ALC_MSIX_MESSAGES 1
+
+#define ALC_TX_RING_SZ \
+ (sizeof(struct tx_desc) * ALC_TX_RING_CNT)
+#define ALC_RX_RING_SZ \
+ (sizeof(struct rx_desc) * ALC_RX_RING_CNT)
+#define ALC_RR_RING_SZ \
+ (sizeof(struct rx_rdesc) * ALC_RR_RING_CNT)
+#define ALC_CMB_SZ (sizeof(struct cmb))
+#define ALC_SMB_SZ (sizeof(struct smb))
+
+#define ALC_PROC_MIN 16
+#define ALC_PROC_MAX (ALC_RX_RING_CNT - 1)
+#define ALC_PROC_DEFAULT (ALC_RX_RING_CNT / 4)
+
+#define ALC_JUMBO_FRAMELEN (9 * 1024)
+#define ALC_JUMBO_MTU \
+ (ALC_JUMBO_FRAMELEN - sizeof(struct ether_vlan_header) - ETHER_CRC_LEN)
+#define ALC_MAX_FRAMELEN (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN)
+
+/*
+ * The number of bits reserved for MSS in AR8121/AR8132 controllers
+ * are 13 bits. This limits the maximum interface MTU size in TSO
+ * case(8191 + sizeof(struct ip) + sizeof(struct tcphdr)) as upper
+ * stack should not generate TCP segments with MSS greater than the
+ * limit. Also Atheros says that maximum MTU for TSO is 6KB.
+ */
+#define ALC_TSO_MTU (6 * 1024)
+
+struct alc_rxdesc {
+ struct mbuf *rx_m;
+ bus_dmamap_t rx_dmamap;
+ struct rx_desc *rx_desc;
+};
+
+struct alc_txdesc {
+ struct mbuf *tx_m;
+ bus_dmamap_t tx_dmamap;
+};
+
+struct alc_ring_data {
+ struct tx_desc *alc_tx_ring;
+ bus_dma_segment_t alc_tx_ring_seg;
+ bus_addr_t alc_tx_ring_paddr;
+ struct rx_desc *alc_rx_ring;
+ bus_dma_segment_t alc_rx_ring_seg;
+ bus_addr_t alc_rx_ring_paddr;
+ struct rx_rdesc *alc_rr_ring;
+ bus_dma_segment_t alc_rr_ring_seg;
+ bus_addr_t alc_rr_ring_paddr;
+ struct cmb *alc_cmb;
+ bus_dma_segment_t alc_cmb_seg;
+ bus_addr_t alc_cmb_paddr;
+ struct smb *alc_smb;
+ bus_dma_segment_t alc_smb_seg;
+ bus_addr_t alc_smb_paddr;
+};
+
+struct alc_chain_data {
+ struct alc_txdesc alc_txdesc[ALC_TX_RING_CNT];
+ struct alc_rxdesc alc_rxdesc[ALC_RX_RING_CNT];
+ bus_dmamap_t alc_tx_ring_map;
+ bus_dma_segment_t alc_tx_ring_seg;
+ bus_dmamap_t alc_rx_ring_map;
+ bus_dma_segment_t alc_rx_ring_seg;
+ bus_dmamap_t alc_rr_ring_map;
+ bus_dma_segment_t alc_rr_ring_seg;
+ bus_dmamap_t alc_rx_sparemap;
+ bus_dmamap_t alc_cmb_map;
+ bus_dma_segment_t alc_cmb_seg;
+ bus_dmamap_t alc_smb_map;
+ bus_dma_segment_t alc_smb_seg;
+
+ int alc_tx_prod;
+ int alc_tx_cons;
+ int alc_tx_cnt;
+ int alc_rx_cons;
+ int alc_rr_cons;
+ int alc_rxlen;
+
+ struct mbuf *alc_rxhead;
+ struct mbuf *alc_rxtail;
+ struct mbuf *alc_rxprev_tail;
+};
+
+struct alc_hw_stats {
+ /* Rx stats. */
+ uint32_t rx_frames;
+ uint32_t rx_bcast_frames;
+ uint32_t rx_mcast_frames;
+ uint32_t rx_pause_frames;
+ uint32_t rx_control_frames;
+ uint32_t rx_crcerrs;
+ uint32_t rx_lenerrs;
+ uint64_t rx_bytes;
+ uint32_t rx_runts;
+ uint32_t rx_fragments;
+ uint32_t rx_pkts_64;
+ uint32_t rx_pkts_65_127;
+ uint32_t rx_pkts_128_255;
+ uint32_t rx_pkts_256_511;
+ uint32_t rx_pkts_512_1023;
+ uint32_t rx_pkts_1024_1518;
+ uint32_t rx_pkts_1519_max;
+ uint32_t rx_pkts_truncated;
+ uint32_t rx_fifo_oflows;
+ uint32_t rx_rrs_errs;
+ uint32_t rx_alignerrs;
+ uint64_t rx_bcast_bytes;
+ uint64_t rx_mcast_bytes;
+ uint32_t rx_pkts_filtered;
+ /* Tx stats. */
+ uint32_t tx_frames;
+ uint32_t tx_bcast_frames;
+ uint32_t tx_mcast_frames;
+ uint32_t tx_pause_frames;
+ uint32_t tx_excess_defer;
+ uint32_t tx_control_frames;
+ uint32_t tx_deferred;
+ uint64_t tx_bytes;
+ uint32_t tx_pkts_64;
+ uint32_t tx_pkts_65_127;
+ uint32_t tx_pkts_128_255;
+ uint32_t tx_pkts_256_511;
+ uint32_t tx_pkts_512_1023;
+ uint32_t tx_pkts_1024_1518;
+ uint32_t tx_pkts_1519_max;
+ uint32_t tx_single_colls;
+ uint32_t tx_multi_colls;
+ uint32_t tx_late_colls;
+ uint32_t tx_excess_colls;
+ uint32_t tx_abort;
+ uint32_t tx_underrun;
+ uint32_t tx_desc_underrun;
+ uint32_t tx_lenerrs;
+ uint32_t tx_pkts_truncated;
+ uint64_t tx_bcast_bytes;
+ uint64_t tx_mcast_bytes;
+};
+
+/*
+ * Software state per device.
+ */
+struct alc_softc {
+ device_t sc_dev;
+ struct ethercom sc_ec;
+
+ bus_space_tag_t sc_mem_bt;
+ bus_space_handle_t sc_mem_bh;
+ bus_size_t sc_mem_size;
+ bus_dma_tag_t sc_dmat;
+ pci_chipset_tag_t sc_pct;
+ pcitag_t sc_pcitag;
+
+ void *sc_irq_handle;
+
+ struct mii_data sc_miibus;
+ int alc_rev;
+ int alc_chip_rev;
+ int alc_phyaddr;
+ uint8_t alc_eaddr[ETHER_ADDR_LEN];
+ uint32_t alc_dma_rd_burst;
+ uint32_t alc_dma_wr_burst;
+ uint32_t alc_rcb;
+ int alc_flags;
+#define ALC_FLAG_PCIE 0x0001
+#define ALC_FLAG_PCIX 0x0002
+#define ALC_FLAG_MSI 0x0004
+#define ALC_FLAG_MSIX 0x0008
+#define ALC_FLAG_FASTETHER 0x0020
+#define ALC_FLAG_JUMBO 0x0040
+#define ALC_FLAG_ASPM_MON 0x0080
+#define ALC_FLAG_CMB_BUG 0x0100
+#define ALC_FLAG_SMB_BUG 0x0200
+#define ALC_FLAG_DETACH 0x4000
+#define ALC_FLAG_LINK 0x8000
+
+ callout_t sc_tick_ch;
+ struct alc_hw_stats alc_stats;
+ struct alc_chain_data alc_cdata;
+ struct alc_ring_data alc_rdata;
+ int alc_int_rx_mod;
+ int alc_int_tx_mod;
+ int alc_buf_size;
+};
+
+/* Register access macros. */
+#define CSR_WRITE_4(_sc, reg, val) \
+ bus_space_write_4((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg), (val))
+#define CSR_WRITE_2(_sc, reg, val) \
+ bus_space_write_2((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg), (val))
+#define CSR_WRITE_1(_sc, reg, val) \
+ bus_space_write_1((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg), (val))
+#define CSR_READ_2(_sc, reg) \
+ bus_space_read_2((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg))
+#define CSR_READ_4(_sc, reg) \
+ bus_space_read_4((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg))
+
+#define ALC_RXCHAIN_RESET(_sc)
\
+do { \
+ (_sc)->alc_cdata.alc_rxhead = NULL; \
+ (_sc)->alc_cdata.alc_rxtail = NULL; \
+ (_sc)->alc_cdata.alc_rxprev_tail = NULL; \
+ (_sc)->alc_cdata.alc_rxlen = 0; \
+} while (0)
+
+#define ALC_TX_TIMEOUT 5
+#define ALC_RESET_TIMEOUT 100
+#define ALC_TIMEOUT 1000
+#define ALC_PHY_TIMEOUT 1000
+
+#endif /* _IF_ALCREG_H */
Attachment:
test_alc.sh
Description: Bourne shell script