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Re: Today's -current no longer boots on my amd64 machine
On 04/20/10 02:03, Joerg Sonnenberger wrote:
On Tue, Apr 20, 2010 at 01:52:30AM +0200, Jean-Yves Migeon wrote:
Yep I know, and I also have to check about the CPUID_NOX feature of cpuid.
I'm not sure that it going to work either. In fact, I am quite sure it
doesn't. You will get a GPF if accessing a page with the NX bit set if
the feature is not active.
Yeah, I saw that yesterday in the AMD docs.
The previous patch sets the EFER_NXE bit after having enabled paging and
I can move it closer to the %cr0 assignement, but not much; the
cpu_feature variable is in 64 bit code, and before the ljmp to
mp_trampoline_end, we are still in 32 bit code; this won't link.
FWIW, the #GP occuring without the patch is due to the idlelwp struct
being allocated in the slow path of a pool_cache, and is very likely to
be marked as NX by BP.
I can move it above the cpu_starting busy wait loop, might give some
delay to the secondary CPU.
RCS file: /cvsroot/src/sys/arch/amd64/amd64/mptramp.S,v
retrieving revision 1.11
diff -u -u -r1.11 mptramp.S
--- sys/arch/amd64/amd64/mptramp.S 18 Apr 2010 23:47:50 -0000 1.11
+++ sys/arch/amd64/amd64/mptramp.S 20 Apr 2010 07:26:33 -0000
@@ -217,6 +217,18 @@
_C_LABEL(cpu_spinup_trampoline_end): #end of code copied to MP_TRAMPOLINE
+ * Without EFER_NXE enabled on the CPU, a set NX bit will raise
+ * a #GP. Avoid that by setting the NXE feature now.
+ movl _C_LABEL(cpu_feature)+2*4,%eax /* cpu_feature */
+ andl $CPUID_NOX,%eax
+ jz 1f
+ movl $MSR_EFER,%ecx
+ orl $EFER_NXE,%eax /* enable No-Execute feature */
/* Don't touch lapic until BP has done init sequence. */
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