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Re: 5.99.15 ale quirks on Asus Eee 1000H
Christoph Egger wrote:
> Malcolm Herbert wrote:
>> I've done an upgrade install on an Asus Eee 1000H ... so far things look
>> like they're going well and the ale device is working, however I'm seeing
>> the following from dmesg during boot and around dhclient startup:
>>
>> |ale0: DMA read error! -- resetting
>> |ale0: could not disable Tx/Rx MAC(0x00000008)!
>> |ale0: DMA read error! -- resetting
>> |ale0: could not disable Tx/Rx MAC(0x00000008)!
>> |ale0: DMA read error! -- resetting
>> |ale0: could not disable Tx/Rx MAC(0x00000008)!
>>
>> The device is up and appears to work OK ... whatever the issue us
>> doesn't appear to affect ssh interactive use, but haven't yet tried to
>> push a lot of data through it, so can't give complete report, sorry
>>
>> Other than that, things seem fine ... still using stock 5.0 X11 as I
>> forgot to build that ... :)
>
> If your NIC is fast ethernet only, then attach patch may help.
Actually this one. Previous had a typo.
Sorry for the inconvinience.
Christoph
Index: if_ale.c
===================================================================
RCS file: /cvsroot/src/sys/dev/pci/if_ale.c,v
retrieving revision 1.5
diff -u -p -r1.5 if_ale.c
--- if_ale.c 5 Aug 2009 07:03:04 -0000 1.5
+++ if_ale.c 5 Aug 2009 07:13:28 -0000
@@ -142,6 +142,17 @@ ale_miibus_readreg(device_t dev, int phy
if (phy != sc->ale_phyaddr)
return 0;
+ if (sc->ale_flags & ALE_FLAG_FASTETHER) {
+ switch (reg) {
+ case MII_100T2CR:
+ case MII_100T2SR:
+ case MII_EXTSR:
+ return 0;
+ default:
+ break;
+ }
+ }
+
CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ |
MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));
for (i = ALE_PHY_TIMEOUT; i > 0; i--) {
@@ -157,7 +168,7 @@ ale_miibus_readreg(device_t dev, int phy
return 0;
}
- return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT);
+ return (v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT;
}
static void
@@ -170,6 +181,17 @@ ale_miibus_writereg(device_t dev, int ph
if (phy != sc->ale_phyaddr)
return;
+ if (sc->ale_flags & ALE_FLAG_FASTETHER) {
+ switch (reg) {
+ case MII_100T2CR:
+ case MII_100T2SR:
+ case MII_EXTSR:
+ return;
+ default:
+ break;
+ }
+ }
+
CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE |
(val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT |
MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));
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