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USB troubles with SB600/SB700 chipsets
Hi,
everyone with an AMD SB600 or SB700 chipset, please test attached patch!
Attached patch is intended to avoid USB subsystem hang symptoms on
all AMD SB600 revisions and AMD SB700 south bridge revision A12 and A13.
The USB subsystem hang symptom is observed when the system has multiple
USB devices connected to it. In some cases a USB hub may be required to
observe this symptom.
This patch works around the problem by correcting the internal register
setting that will help by changing the behavior of the internal logic to
avoid the USB subsystem hang issue. The change in the behavior of the
logic does not impact the normal operation of the USB subsystem.
This should also address PR 40056
(I put the submitter of PR 40056 on CC).
In order to test this patch,
apply the patch and add to the kernel config
amdehci* at pci? dev ? function ?
and when you boot, you should see
amdehci0 at pci
instead of
ehci0 at pci
in the dmesg. Then test if you still encounter any USB problems.
Christoph
Index: sys/dev/pci/amdehci_pci.c
===================================================================
RCS file: sys/dev/pci/amdehci_pci.c
diff -N sys/dev/pci/amdehci_pci.c
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ sys/dev/pci/amdehci_pci.c 17 May 2009 20:38:21 -0000
@@ -0,0 +1,421 @@
+/* $NetBSD: $ */
+
+/*
+ * Copyright (c) 2009 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * Christoph Egger (cegger%NetBSD.org@localhost)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+#include <sys/device.h>
+#include <sys/proc.h>
+#include <sys/queue.h>
+
+#include <sys/bus.h>
+
+#include <dev/pci/pcidevs.h>
+#include <dev/pci/pcivar.h>
+#include <dev/pci/usb_pci.h>
+
+#include <dev/usb/usb.h>
+#include <dev/usb/usbdi.h>
+#include <dev/usb/usbdivar.h>
+#include <dev/usb/usb_mem.h>
+
+#include <dev/usb/ehcireg.h>
+#include <dev/usb/ehcivar.h>
+
+#ifdef EHCI_DEBUG
+#define DPRINTF(x) if (ehcidebug) printf x
+extern int ehcidebug;
+#else
+#define DPRINTF(x)
+#endif
+
+static void amdehci_release_ownership(ehci_softc_t *, pci_chipset_tag_t,
pcitag_t);
+static void amdehci_get_ownership(ehci_softc_t *, pci_chipset_tag_t, pcitag_t);
+static bool amdehci_suspend(device_t PMF_FN_PROTO);
+static bool amdehci_resume(device_t PMF_FN_PROTO);
+
+struct amdehci_softc {
+ ehci_softc_t sc;
+ pci_chipset_tag_t sc_pc;
+ pcitag_t sc_tag;
+ void *sc_ih; /* interrupt vectoring */
+};
+
+#define EHCI_MAX_BIOS_WAIT 1000 /* ms */
+
+static int amdehci_match(device_t, cfdata_t, void *);
+static void amdehci_attach(device_t, device_t, void *);
+static int amdehci_detach(device_t, int);
+
+CFATTACH_DECL3_NEW(amdehci, sizeof(struct amdehci_softc),
+ amdehci_match, amdehci_attach, amdehci_detach, ehci_activate, NULL,
+ ehci_childdet, DVF_DETACH_SHUTDOWN);
+
+static int
+amdehci_sb700_match(struct pci_attach_args *pa)
+{
+ if (!(PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ATI &&
+ PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ATI_SB600_SMB))
+ return 0;
+
+ switch (PCI_REVISION(pa->pa_id)) {
+ case 0x3a:
+ case 0x3b:
+ return 1;
+ }
+
+ return 0;
+}
+
+static int
+amdehci_match(device_t parent, cfdata_t match, void *aux)
+{
+ struct pci_attach_args *pa = (struct pci_attach_args *) aux;
+
+ if (!(PCI_CLASS(pa->pa_class) == PCI_CLASS_SERIALBUS &&
+ PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_SERIALBUS_USB &&
+ PCI_INTERFACE(pa->pa_class) == PCI_INTERFACE_EHCI &&
+ PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ATI))
+ return 0;
+
+ switch (PCI_PRODUCT(pa->pa_id)) {
+ case PCI_PRODUCT_ATI_SB600_USB_EHCI:
+ return 10; /* beat ehci_pci */
+ case PCI_PRODUCT_ATI_SB700_USB_EHCI:
+ if (pci_find_device(NULL, amdehci_sb700_match))
+ return 10; /* beat ehci_pci */
+ default:
+ return 0;
+ }
+}
+
+static int
+amdehci_applyquirks(struct amdehci_softc *sc)
+{
+ uint8_t value;
+
+ aprint_normal_dev(sc->sc.sc_dev,
+ "applying AMD SB600/SB700 USB freeze workaround\n");
+ value = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x53);
+ pci_conf_write(sc->sc_pc, sc->sc_tag, 0x53, value | (1U << 3));
+
+ return 0;
+}
+
+static void
+amdehci_attach(device_t parent, device_t self, void *aux)
+{
+ struct amdehci_softc *sc = device_private(self);
+ struct pci_attach_args *pa = (struct pci_attach_args *)aux;
+ pci_chipset_tag_t pc = pa->pa_pc;
+ pcitag_t tag = pa->pa_tag;
+ char const *intrstr;
+ pci_intr_handle_t ih;
+ pcireg_t csr;
+ const char *vendor;
+ char devinfo[256];
+ usbd_status r;
+ int ncomp;
+ struct usb_pci *up;
+
+ sc->sc.sc_dev = self;
+ sc->sc.sc_bus.hci_private = sc;
+
+ aprint_naive(": AMD SB600/SB700 EHCI controller\n");
+
+ pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo));
+ aprint_normal(": %s (rev. 0x%02x)\n", devinfo,
+ PCI_REVISION(pa->pa_class));
+
+ /* Map I/O registers */
+ if (pci_mapreg_map(pa, PCI_CBMEM, PCI_MAPREG_TYPE_MEM, 0,
+ &sc->sc.iot, &sc->sc.ioh, NULL, &sc->sc.sc_size)) {
+ sc->sc.sc_size = 0;
+ aprint_error_dev(self, "can't map memory space\n");
+ return;
+ }
+
+ /* Disable interrupts, so we don't get any spurious ones. */
+ sc->sc.sc_offs = EREAD1(&sc->sc, EHCI_CAPLENGTH);
+ DPRINTF(("%s: offs=%d\n", device_xname(self), sc->sc.sc_offs));
+ EOWRITE2(&sc->sc, EHCI_USBINTR, 0);
+
+ sc->sc_pc = pc;
+ sc->sc_tag = tag;
+ sc->sc.sc_bus.dmatag = pa->pa_dmat;
+
+ /* Enable the device. */
+ csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
+ pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG,
+ csr | PCI_COMMAND_MASTER_ENABLE);
+
+ /* Map and establish the interrupt. */
+ if (pci_intr_map(pa, &ih)) {
+ aprint_error_dev(self, "couldn't map interrupt\n");
+ goto fail;
+ }
+
+ /*
+ * Allocate IRQ
+ */
+ intrstr = pci_intr_string(pc, ih);
+ sc->sc_ih = pci_intr_establish(pc, ih, IPL_USB, ehci_intr, sc);
+ if (sc->sc_ih == NULL) {
+ aprint_error_dev(self, "couldn't establish interrupt");
+ if (intrstr != NULL)
+ aprint_error(" at %s", intrstr);
+ aprint_error("\n");
+ return;
+ }
+ aprint_normal_dev(self, "interrupting at %s\n", intrstr);
+
+ switch(pci_conf_read(pc, tag, PCI_USBREV) & PCI_USBREV_MASK) {
+ case PCI_USBREV_PRE_1_0:
+ case PCI_USBREV_1_0:
+ case PCI_USBREV_1_1:
+ sc->sc.sc_bus.usbrev = USBREV_UNKNOWN;
+ aprint_verbose_dev(self, "pre-2.0 USB rev\n");
+ return;
+ case PCI_USBREV_2_0:
+ sc->sc.sc_bus.usbrev = USBREV_2_0;
+ break;
+ default:
+ sc->sc.sc_bus.usbrev = USBREV_UNKNOWN;
+ break;
+ }
+
+ /* Figure out vendor for root hub descriptor. */
+ vendor = pci_findvendor(pa->pa_id);
+ sc->sc.sc_id_vendor = PCI_VENDOR(pa->pa_id);
+ if (vendor)
+ strlcpy(sc->sc.sc_vendor, vendor, sizeof(sc->sc.sc_vendor));
+ else
+ snprintf(sc->sc.sc_vendor, sizeof(sc->sc.sc_vendor),
+ "vendor 0x%04x", PCI_VENDOR(pa->pa_id));
+
+ /* Enable workaround for dropped interrupts as required */
+ switch (sc->sc.sc_id_vendor) {
+ case PCI_VENDOR_ATI:
+ case PCI_VENDOR_VIATECH:
+ sc->sc.sc_flags |= EHCIF_DROPPED_INTR_WORKAROUND;
+ aprint_normal_dev(self, "dropped intr workaround enabled\n");
+ break;
+ default:
+ break;
+ }
+
+ /*
+ * Find companion controllers. According to the spec they always
+ * have lower function numbers so they should be enumerated already.
+ */
+ ncomp = 0;
+ TAILQ_FOREACH(up, &ehci_pci_alldevs, next) {
+ if (up->bus == pa->pa_bus && up->device == pa->pa_device) {
+ DPRINTF(("ehci_pci_attach: companion %s\n",
+ device_xname(up->usb)));
+ sc->sc.sc_comps[ncomp++] = up->usb;
+ if (ncomp >= EHCI_COMPANION_MAX)
+ break;
+ }
+ }
+ sc->sc.sc_ncomp = ncomp;
+
+ amdehci_get_ownership(&sc->sc, pc, tag);
+
+ amdehci_applyquirks(sc);
+
+ r = ehci_init(&sc->sc);
+ if (r != USBD_NORMAL_COMPLETION) {
+ aprint_error_dev(self, "init failed, error=%d\n", r);
+ goto fail;
+ }
+
+ /* Attach usb device. */
+ sc->sc.sc_child = config_found(self, &sc->sc.sc_bus, usbctlprint);
+
+ if (!pmf_device_register1(self, amdehci_suspend, amdehci_resume,
+ ehci_shutdown))
+ aprint_error_dev(self, "couldn't establish power handler\n");
+
+ /* Attach usb device. */
+ sc->sc.sc_child = config_found(self, &sc->sc.sc_bus, usbctlprint);
+ return;
+
+fail:
+ if (sc->sc_ih) {
+ pci_intr_disestablish(sc->sc_pc, sc->sc_ih);
+ sc->sc_ih = NULL;
+ }
+ if (sc->sc.sc_size) {
+ amdehci_release_ownership(&sc->sc, sc->sc_pc, sc->sc_tag);
+ bus_space_unmap(sc->sc.iot, sc->sc.ioh, sc->sc.sc_size);
+ sc->sc.sc_size = 0;
+ }
+ return;
+}
+
+static int
+amdehci_detach(device_t self, int flags)
+{
+ struct amdehci_softc *sc = device_private(self);
+ int rv;
+
+ pmf_device_deregister(self);
+ rv = ehci_detach(&sc->sc, flags);
+ if (rv)
+ return rv;
+
+ /* disable interrupts */
+ EOWRITE2(&sc->sc, EHCI_USBINTR, 0);
+ /* XXX grotty hack to flush the write */
+ (void)EOREAD2(&sc->sc, EHCI_USBINTR);
+
+ if (sc->sc_ih != NULL) {
+ pci_intr_disestablish(sc->sc_pc, sc->sc_ih);
+ sc->sc_ih = NULL;
+ }
+ if (sc->sc.sc_size) {
+ amdehci_release_ownership(&sc->sc, sc->sc_pc, sc->sc_tag);
+ bus_space_unmap(sc->sc.iot, sc->sc.ioh, sc->sc.sc_size);
+ sc->sc.sc_size = 0;
+ }
+
+ return 0;
+}
+
+static void
+amdehci_release_ownership(ehci_softc_t *sc, pci_chipset_tag_t pc, pcitag_t tag)
+{
+ const char *devname = device_xname(sc->sc_dev);
+ uint32_t cparams, addr, cap;
+ pcireg_t legsup;
+ int maxcap = 10;
+
+ cparams = EREAD4(sc, EHCI_HCCPARAMS);
+ addr = EHCI_HCC_EECP(cparams);
+ while (addr != 0) {
+ cap = pci_conf_read(pc, tag, addr);
+ if (EHCI_CAP_GET_ID(cap) != EHCI_CAP_ID_LEGACY)
+ goto next;
+ legsup = pci_conf_read(pc, tag, addr + PCI_EHCI_USBLEGSUP);
+ pci_conf_write(pc, tag, addr + PCI_EHCI_USBLEGSUP,
+ legsup & ~EHCI_LEG_HC_OS_OWNED);
+
+next:
+ if (--maxcap < 0) {
+ aprint_normal("%s: broken extended capabilities "
+ "ignored\n", devname);
+ return;
+ }
+ addr = EHCI_CAP_GET_NEXT(cap);
+ }
+}
+
+static void
+amdehci_get_ownership(ehci_softc_t *sc, pci_chipset_tag_t pc, pcitag_t tag)
+{
+ const char *devname = device_xname(sc->sc_dev);
+ uint32_t cparams, addr, cap;
+ pcireg_t legsup;
+ int maxcap = 10;
+ int ms;
+
+#ifdef EHCI_DEBUG
+ if (ehcidebug)
+ ehci_dump_caps(sc, pc, tag);
+#endif
+ cparams = EREAD4(sc, EHCI_HCCPARAMS);
+ addr = EHCI_HCC_EECP(cparams);
+ while (addr != 0) {
+ cap = pci_conf_read(pc, tag, addr);
+ if (EHCI_CAP_GET_ID(cap) != EHCI_CAP_ID_LEGACY)
+ goto next;
+ legsup = pci_conf_read(pc, tag, addr + PCI_EHCI_USBLEGSUP);
+ /* Ask BIOS to give up ownership */
+ pci_conf_write(pc, tag, addr + PCI_EHCI_USBLEGSUP,
+ legsup | EHCI_LEG_HC_OS_OWNED);
+ if (legsup & EHCI_LEG_HC_BIOS_OWNED) {
+ for (ms = 0; ms < EHCI_MAX_BIOS_WAIT; ms++) {
+ legsup = pci_conf_read(pc, tag,
+ addr + PCI_EHCI_USBLEGSUP);
+ if (!(legsup & EHCI_LEG_HC_BIOS_OWNED))
+ break;
+ delay(1000);
+ }
+ if (ms == EHCI_MAX_BIOS_WAIT) {
+ aprint_normal("%s: BIOS refuses to give up "
+ "ownership, using force\n", devname);
+ pci_conf_write(pc, tag,
+ addr + PCI_EHCI_USBLEGSUP, 0);
+ } else
+ aprint_verbose("%s: BIOS has given up "
+ "ownership\n", devname);
+ }
+
+ /* Disable SMIs */
+ pci_conf_write(pc, tag, addr + PCI_EHCI_USBLEGCTLSTS,
+ EHCI_LEG_EXT_SMI_BAR | EHCI_LEG_EXT_SMI_PCICMD |
+ EHCI_LEG_EXT_SMI_OS_CHANGE);
+
+next:
+ if (--maxcap < 0) {
+ aprint_normal("%s: broken extended capabilities "
+ "ignored\n", devname);
+ return;
+ }
+ addr = EHCI_CAP_GET_NEXT(cap);
+ }
+
+}
+
+static bool
+amdehci_suspend(device_t dv PMF_FN_ARGS)
+{
+ struct amdehci_softc *sc = device_private(dv);
+
+ ehci_suspend(dv PMF_FN_CALL);
+ amdehci_release_ownership(&sc->sc, sc->sc_pc, sc->sc_tag);
+
+ return true;
+}
+
+static bool
+amdehci_resume(device_t dv PMF_FN_ARGS)
+{
+ struct amdehci_softc *sc = device_private(dv);
+
+ amdehci_get_ownership(&sc->sc, sc->sc_pc, sc->sc_tag);
+ return ehci_resume(dv PMF_FN_CALL);
+}
+
Index: sys/dev/pci/files.pci
===================================================================
RCS file: /cvsroot/src/sys/dev/pci/files.pci,v
retrieving revision 1.314
diff -u -p -r1.314 files.pci
--- sys/dev/pci/files.pci 21 Apr 2009 03:00:29 -0000 1.314
+++ sys/dev/pci/files.pci 17 May 2009 20:38:21 -0000
@@ -594,6 +594,11 @@ file dev/pci/ehci_pci.c ehci_pci
file dev/pci/usb_pci.c ehci_pci | ehci_cardbus
+# AMD SB600/SB700 EHCI USB controller
+device amdehci: usbus, usbroothub
+attach amdehci at pci
+file dev/pci/amdehci_pci.c amdehci
+
# OHCI IEEE 1394 controller
attach fwohci at pci with fwohci_pci
file dev/pci/fwohci_pci.c fwohci_pci
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