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Re: satalink at cardbus

> > OK, I've found something a little disturbing: when the card is
> > inserted after the system boots up, everything is fine. If the card
> > is present at boot time, however, I get an NMI and a drop into the
> > debugger. If I continue, then everything works as mostly normal - but
> > there's sometimes a hang during reboot.
> It looks like you have an O2 Micro CardBus bridge.  O2 Micro bridges will
> spuriously indicate a bus error if parity-error detection is activated.
> The error should be apparent in the pcictl(8) dump of the bridge.
> I will commit a patch to treat your particular bridge (vendor 0x1217
> product 0x7223), soon.

This is borne out by the fact that this behavior only happens on one
machine I have - and that I get the same behavior after insertion of
the card and also trying to access any of the connected drives.

Here's the pcictl dump.

PCI configuration registers:
  Common header:
    0x00: 0x72231217 0x441001c7 0x06070000 0x00824000

    Vendor Name: O2 Micro (0x1217)
    Device ID: 0x7223
    Command register: 0x01c7
      I/O space accesses: on
      Memory space accesses: on
      Bus mastering: on
      Special cycles: off
      MWI transactions: off
      Palette snooping: off
      Parity error checking: on
      Address/data stepping: on
      System error (SERR): on
      Fast back-to-back transactions: off
      Interrupt disable: off
    Status register: 0x4410
      Capability List support: on
      66 MHz capable: off
      User Definable Features (UDF) support: off
      Fast back-to-back capable: off
      Data parity error detected: off
      DEVSEL timing: slow (0x2)
      Slave signaled Target Abort: off
      Master received Target Abort: off
      Master received Master Abort: off
      Asserted System Error (SERR): on
      Parity error detected: off
    Class Name: bridge (0x06)
    Subclass Name: CardBus (0x07)
    Interface: 0x00
    Revision ID: 0x00
    BIST: 0x00
    Header Type: 0x02+multifunction (0x82)
    Latency Timer: 0x40
    Cache Line Size: 0x00

  Type 2 (PCI-CardBus bridge) header:
    0x10: 0x90100000 0x020000a0 0x20030302 0x40000000
    0x20: 0x40000000 0xfffff000 0x00000000 0x00004301
    0x30: 0x00004f05 0x00005301 0x00005301 0x0403010a
    0x40: 0x0890103c 0x00000001

    Base address register at 0x10 (CardBus socket/ExCA registers)
      type: 32-bit nonprefetchable memory
      base: 0x90100000, not sized
    Capability list pointer: 0xa0
    Secondary status register: 0x0200
      66 MHz capable: off
      User Definable Features (UDF) support: off
      Fast back-to-back capable: off
      Data parity error detection: off
      DEVSEL timing: medium (0x1)
      PCI target aborts terminate CardBus bus master transactions: off
      CardBus target aborts terminate PCI bus master transactions: off
      Bus initiator aborts terminate initiator transactions: off
      System error: off
      Parity error: off
    PCI bus number: 0x02
    CardBus bus number: 0x03
    Subordinate bus number: 0x03
    CardBus latency timer: 0x20
    CardBus memory region 0:
      base register:  0x40000000
      limit register: 0x40000000
    CardBus memory region 1:
      base register:  0xfffff000
      limit register: 0x00000000
    CardBus I/O region 0:
      base register:  0x00004301
      limit register: 0x00004f05
    CardBus I/O region 1:
      base register:  0x00005301
      limit register: 0x00005301
    Interrupt line: 0x0a
    Interrupt pin: 0x01 (pin A)
    Bridge control register: 0x0403
      Parity error response: on
      CardBus SERR forwarding: on
      ISA enable: off
      VGA enable: off
      CardBus master abort reporting: off
      CardBus reset: off
      Functional interrupts routed by ExCA registers: off
      Memory window 0 prefetchable: off
      Memory window 1 prefetchable: off
      Write posting enable: on
    Subsystem vendor ID: 0x103c
    Subsystem ID: 0x0890
    Base address register at 0x44 (legacy-mode registers)
      type: i/o
      base: 0x00000000, not sized

  Capability register at 0xa0
    type: 0x01 (Power Management, rev. 1.0)

  Device-dependent header:
    0x48: 0x00000000 0x00000000
    0x50: 0x00000000 0x00000000 0x00000000 0x00000000
    0x60: 0x00000000 0x00000000 0x00000000 0x00000000
    0x70: 0x00000000 0x00000000 0x00000000 0x00000000
    0x80: 0x00000000 0x00000000 0x00000000 0x00000000
    0x90: 0x08002000 0x80620bea 0x00400000 0x00050003
    0xa0: 0xfe020001 0x10c04000 0x00000000 0x00000000
    0xb0: 0x00000000 0x00000000 0x00000000 0x00000000
    0xc0: 0x00000000 0x00000000 0x00000000 0x00000000
    0xd0: 0x00000000 0x00000000 0x00000000 0x00030000
    0xe0: 0x00000000 0x00000000 0x00000000 0x00000000
    0xf0: 0x00000000 0x00000000 0x00000000 0x00000000

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