Re: tlp(4) DMA synchronization

[Jason Thorpe <thorpej%shagadelic.org@localhost>]

On Aug 27, 2009, at 4:57 PM, David Young wrote:

> We may be able to use cacheline-aligned descriptors in ring mode if  
> the
> chip respects the Descriptor Skip Length (DSL) field of the Bus Mode
> Register.  According to the datasheet, the DSL field "Specifies the
> number of longwords to skip between two unchained descriptors."
>
> What do you think?

Sorry this is late...

Not all of the clones support DSL, and not all of the clones support  
chain mode.

-- thorpej