tech-net archive

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index][Old Index]

Re: tlp(4) DMA synchronization

> I made a patch to complete/optimize DMA synchronization in tlp(4),
> does it look correct?  URL:

>> +                    TULIP_CDRXSYNC(sc, i,
>> +                        BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
>> +            if (txstat & TDSTAT_OWN) {
>> +                    TULIP_CDTXSYNC(sc, txs->txs_lastdesc, 1,
>> +                        BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);

Only BUS_DMASYNC_PREREAD is enough because
no write (host -> device) op will happen after
these pollings.

These ops are required on systems which don't handle BUS_DMA_COHERENT.
But strictly speaking, on such system we'd have to use chained mode
(not ring mode) with proper padded between each DMA descriptor,
i.e. one descriptor per cacheline to avoid host vs DMA race.
Izumi Tsutsui

Home | Main Index | Thread Index | Old Index