Re: CVS commit: src/sys/arch

[Rin Okuyama <rokuyama.rk%gmail.com@localhost>]

Thanks for quick response. Committed :)

rin

On 2021/10/11 16:27, Nick Hudson wrote:
> On 11/10/2021 08:14, Rin Okuyama wrote:
> > Hi,
> >
> > On 2021/09/23 15:34, Nick Hudson wrote:
> > > Module Name:    src
> > > Committed By:    skrll
> > > Date:        Thu Sep 23 06:34:00 UTC 2021
> > >
> > > Modified Files:
> > >     src/sys/arch/aarch64/aarch64: cpufunc.c
> > >     src/sys/arch/arm/arm32: cpu.c
> > >
> > > Log Message:
> > > Print the cache information in similar formats and arm and aarch64, e.g.
> >
> > For classic ARM CPUs, info->[id]cache_sets are not set. This results in
> >
> > cpu0 at mainbus0 core 0: SA-1110 step B-5 (SA-1 V4 core)
> > cpu0: DC enabled IC enabled WB enabled LABT
> > cpu0: L1 16KB/32B 32-way (0 set) VIVT Instruction cache
> > cpu0: L1 8KB/32B 32-way (0 set) write-back VIVT Data cache
> >
> > or
> >
> > cpu0 at mainbus0 core 0: ARM926EJ-S r0p0 (ARM9EJ-S V5TEJ core)
> > cpu0: DC enabled IC enabled WB enabled LABT
> > cpu0: L1 32KB/32B 1-way (0 set) VIVT Instruction cache
> > cpu0: L1 32KB/32B 1-way (0 set) write-back-locking-C VIVT Data cache
> >
> > Can I commit the attached patch? Or initialize these variables somewhere
> > else?
>
> I think your patch is fine. Thanks for fixing this.
>
> Nick