Re: CVS commit: src/sys/arch

[Rin Okuyama <rokuyama.rk%gmail.com@localhost>]

Hi,

On 2021/09/23 15:34, Nick Hudson wrote:
> Module Name:	src
> Committed By:	skrll
> Date:		Thu Sep 23 06:34:00 UTC 2021
>
> Modified Files:
> 	src/sys/arch/aarch64/aarch64: cpufunc.c
> 	src/sys/arch/arm/arm32: cpu.c
>
> Log Message:
> Print the cache information in similar formats and arm and aarch64, e.g.

For classic ARM CPUs, info->[id]cache_sets are not set. This results in

cpu0 at mainbus0 core 0: SA-1110 step B-5 (SA-1 V4 core)
cpu0: DC enabled IC enabled WB enabled LABT
cpu0: L1 16KB/32B 32-way (0 set) VIVT Instruction cache
cpu0: L1 8KB/32B 32-way (0 set) write-back VIVT Data cache

or

cpu0 at mainbus0 core 0: ARM926EJ-S r0p0 (ARM9EJ-S V5TEJ core)
cpu0: DC enabled IC enabled WB enabled LABT
cpu0: L1 32KB/32B 1-way (0 set) VIVT Instruction cache
cpu0: L1 32KB/32B 1-way (0 set) write-back-locking-C VIVT Data cache

Can I commit the attached patch? Or initialize these variables somewhere else?

Thanks,
rin

Index: sys/arch/arm/arm32/cpu.c
===================================================================
RCS file: /home/netbsd/src/sys/arch/arm/arm32/cpu.c,v
retrieving revision 1.149
diff -p -u -r1.149 cpu.c
--- sys/arch/arm/arm32/cpu.c	23 Sep 2021 06:34:00 -0000	1.149
+++ sys/arch/arm/arm32/cpu.c	8 Oct 2021 00:11:34 -0000
@@ -612,7 +612,9 @@ print_cache_info(device_t dv, struct arm
 		    level + 1,
 		    info->dcache_size / 1024,
 		    info->dcache_line_size, info->dcache_ways,
-		    info->dcache_sets,
+		    info->dcache_sets ? info->dcache_sets :
+			info->dcache_size /
+			    (info->dcache_line_size * info->dcache_ways),
 		    wtnames[info->cache_type],
 		    info->dcache_type & CACHE_TYPE_PIxx ? 'P' : 'V',
 		    info->dcache_type & CACHE_TYPE_xxPT ? 'P' : 'V');
@@ -621,14 +623,18 @@ print_cache_info(device_t dv, struct arm
 		    level + 1,
 		    info->icache_size / 1024,
 		    info->icache_line_size, info->icache_ways,
-		    info->icache_sets,
+		    info->icache_sets ? info->icache_sets :
+			info->icache_size /
+			    (info->icache_line_size * info->icache_ways),
 		    info->icache_type & CACHE_TYPE_PIxx ? 'P' : 'V',
 		    info->icache_type & CACHE_TYPE_xxPT ? 'P' : 'V');
 		aprint_normal_dev(dv, "L%u %dKB/%dB %d-way (%u set) %s %cI%cT Data cache\n",
 		    level + 1,
 		    info->dcache_size / 1024,
 		    info->dcache_line_size, info->dcache_ways,
-		    info->dcache_sets,
+		    info->dcache_sets ? info->dcache_sets :
+			info->dcache_size /
+			    (info->dcache_line_size * info->dcache_ways),
 		    wtnames[info->cache_type],
 		    info->dcache_type & CACHE_TYPE_PIxx ? 'P' : 'V',
 		    info->dcache_type & CACHE_TYPE_xxPT ? 'P' : 'V');