On 20/08/15 22:20, Mouse wrote:
The document I have makes it sound as though there are no "systems
which support both flavours" - it's written as though the
interpretation of the low 25 bits of a PTE is an intrinsic property of
a particular VAX processor, just as tied to the implementation as
(say) whether MOVTC runs in hardware or takes an instruction-emulation
trap.
After describing the 32-bit PA layout, the NVAX Plus CPU Chip Functional
Specification goes on to say:
"In addition to the natural 32-bit physical address, the CPU may be
configured to generate 30-bit
physical addresses. In this mode, only 512MB of memory space can be
referenced, as shown in
Figure 2–3."
So it _sounds_ as though NVAX+ could be configured in either mode.
Somewhere or other I'm sure I have the documents that were used when the
WAN Device Drivers needed
to be tweaked to cope with the associated VMS changes. That's the
document (or documents) that I
was looking for when I ran into the NVAX+ spec (which should be on the
web somewhere iirc).