Re: Porting to IBM Risc 6000

[Matt Thomas <matt%3am-software.com@localhost>]

At 07:39 AM 8/9/2002, David Edelsohn wrote:
> >>>>> Matt Thomas writes:
>
> Matt> Does Power3 follow the OEA 64-bit manual for memory management?  Does it
> Matt> do the 32-bit and 64-bit bridges?
>
>         Power3 supports the OEA and includes the 64-bit bridge mode
> instructions.

That simplifies things a lot.

> Matt> If so, it seems the only significant difference is the replacement
> Matt> of the segment register with the segment descriptor elements and the
> Matt> Address Space Register.   I assume I need to do a "slbia" when changing
> Matt> the ASR register (aka process switching).  Or just update the active
> Matt> SDE's on a stack switch (which would prevent having to flush the kernel
> Matt> SDE entries from the SLB).
>
>         64-bit bridge mode includes backward compatibility for segment
> registers (suitably expanded), so one does not need to deal with the
> entire segment descriptor infrastructure and the lack of BATs.

No BATs?  Eek.  Hmmm.  Thinking about it.  Since NetBSD/powerpc on OEA
doesn't support LKMs so the only executeable code is from kernel text,
I'm just starting to wonder we use IBAT0 to map the low 256MB of RAM.
Why not just run with PSL_IR (instruction relocation off)?  That removes
the need for that BAT.  That leaves kernel text(.rodata)/data/bss.

I'd love to be actually nice to put those in the page table with appropriate
protection bits.  Even on 32-bit platforms.  Just imagine the bugs that
could be caught.

--
Matt Thomas               Internet:   matt%3am-software.com@localhost
3am Software Foundry      WWW URL:    http://www.3am-software.com/bio/matt/
Cupertino, CA             Disclaimer: I avow all knowledge of this message