Re: Porting to IBM Risc 6000

[Matt Thomas <matt%3am-software.com@localhost>]

At 11:00 AM 8/8/2002, David Edelsohn wrote:
> >>>>> matthew green writes:
>
> matthew> is that really logically any different that 32-bit on sparc64
> matthew> hardware, where many supervisor parts are 64-bits?  ie, it only
> matthew> requires special assembler code, not a real 64 bit kernel?
>
>         I do not know what was done for 32-bit FreeBSD on Sparc64.
>
>         A 64-bit PowerPC kernel should only require a few 64-bit PowerPC
> assembly routines to manipulate the registers.

Does Power3 follow the OEA 64-bit manual for memory management?  Does it
do the 32-bit and 64-bit bridges?

If so, it seems the only significant difference is the replacement
of the segment register with the segment descriptor elements and the
Address Space Register.   I assume I need to do a "slbia" when changing
the ASR register (aka process switching).  Or just update the active
SDE's on a stack switch (which would prevent having to flush the kernel
SDE entries from the SLB).

Of course, now that there is 64bits of address space (and those having
to invalidate the SLB when going into the kernel each time), it seems
reasonable to split the address space between user and kernel ranges.
I was thinking reserving 0xffff.0000.0000.0000 and above for the kernel.
I think that will be enough. :)

When running a 32-bit kernel, it may be best to do the "slbia" and take
the hit and have a kernel-only SLB and use our current method of bat
paging.

--
Matt Thomas               Internet:   matt%3am-software.com@localhost
3am Software Foundry      WWW URL:    http://www.3am-software.com/bio/matt/
Cupertino, CA             Disclaimer: I avow all knowledge of this message