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Re: Delay slots
On Tue, 21 Jun 2016, Warner Losh wrote:
> For MIPS the list of instructions is simple. There’s the branch delay slot
> which always executes while the jump is happening. This is well know
> and everybody takes advantage of it to ‘hide’ the loading of args to functions
> or do other useful work. On mips1, there’s also the load delay slot, which
> means you can’t use the result of the load for 1 instruction.
> That’s it.
You missed coprocessor move delay slots, MIPS I-III. E.g. you need to
schedule a NOP between these pairs of instructions each if you don't have
anything useful to put there:
cfc1 $2, $31
andi $3, $2, 0x4
mfc1 $2, $f0
bltz $2, foo
dmtc1 $2, $f0
div.d $f2, $f1, $f0
mfc0 $2, $15
srl $3, $2, 16
Needless to say GAS handles all of this automagically in the `reorder'
NB none of this qualifies as a hazard in MIPS-speak, these are all plain
late data delivery cases, due to the absence of interlocking or a bypass
(as with memory loads from MIPS II up) in the pipeline.
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