Re: Delay slots

[<Paul_Koning%Dell.com@localhost>]

> On Jun 11, 2016, at 1:23 PM, coypu%SDF.ORG@localhost wrote:
> 
> Hi,
> 
> I've heard port-pmax has trouble with mfc0 instruction needing a delay
> slot after it, and the generic MIPS code being modified and tested
> against newer machines which do not need this.
> 
> Delay slots are a generic MIPS problem, 
> ...
> If someone could provide a useful list of problematic instructions and
> mention architectures suffering problems, this could be a good tool.

I think "delay slot" is a specific term with a different meaning.  Mostly it refers to the bizarre handling of the instruction immediately following a branch instruction (other than branch-likely). In MIPS-1 it also shows up in loads, but that disappeared a very long time ago.

What you're talking about I know as a "hazard" -- a machine-specific rule that says after some privileged instructions you need to do extra stuff before looking for a result, or expecting the action to take effect, or whatever.  That extra stuff might be NOP instructions, SSNOP instructions, or even weirder things.

This is all specific to individual machine implementations.  A generic list would have to be the union of all hazards, which is going to be quite a long list.  Some machines have very few; others (such as the Sibyte chips) have a rather substantial set.  In some cases, specific chip revs have even more hazards and particularly bizarre rules because you're actually looking at chip bugs and their workarounds.

So my answer would be: read the specific machine data sheet or programming manual for the hazards.  Hopefully they are described correctly and completely.  (Some vendors assign data sheet writing to the marketing department, so the English is pretty good but the technical content is not.)  You may need to find the "errata" for the product in question; access to that information may be hard to get at times.

	paul