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Re: Delay slots

>>> Delay slots are a generic MIPS problem, [...]
> Not a generic MIPS problem - sparc has delay slots too,

I suspect "generic MIPS problem" meant "applying to all MIPS CPUs", not
"restricted to MIPS".  (I didn't write it, though, so I'm not sure.)

> I'm not sure about other architectures but I guess the reason why
> they exist don't apply to just MIPS and SPARC.

Right.  For example, the Super-H, such as is used by NetBSD/dreamcast,
also has delay slots.

> IIRC powerpc needs sync or some delay after writes to certain
> internal registers ( "writes to x take effect after n clock cycles"
> or so ).

The Super-H has similar lossage.  Here, for example, is a comment from
one of my Dreamcast programs (written in assembly to run on the bare

        ; Now running in P2, so we can turn on the cache.
        SETS.L  #CCR,r0
        SETS.L  #CCR_CONFIG,r9
        mov.l   r9,@r0
        ; The hardware PDF, page 77, says that "After CCR is updated,
        ; an instruction that performs data access to the P0, P1, P3,
        ; or U0 area should be located at least four instructions after
        ; the CCR update instruction.  Also, a branch instruction to
        ; the P0, P1, P3, or U0 area should be located at least eight
        ; instructions after the CCR update instruction."  It doesn't
        ; say why this is "should" rather than "must", nor does it
        ; describe the consequences if this is not done, nor does it
        ; say whether this "beyond" refers to address space or
        ; instruction execution order (eg, does a three-instruction
        ; loop that's executed three times count as nine instructions
        ; or three? does a branch seven instructions forward count?).
        ; We treat it pessimistically, making sure we burn eight
        ; instructions by any of these measures.
        ; Gotta love incomplete doc.
        mova    cacheon,r0      ; #1
        SETS.L  #P1_BITS,r9     ; #2
        and     r8,r0           ; #3
        or      r9,r0           ; #4
        mov.l   9f,r15          ; #5
        nop                     ; #6
        nop                     ; #7
        nop                     ; #8

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