Re: x86 bus_dmamap_sync

[Robert Elz <kre%munnari.OZ.AU@localhost>]

    Date:        Sat, 28 Oct 2017 21:26:18 +0200
    From:        Manuel Bouyer <bouyer%antioche.eu.org@localhost>
    Message-ID:  <20171028192618.GA9614%antioche.eu.org@localhost>

  | But I'm not sure that without *fence insctructions, two writes to the
  | same location (or close locations) will be seen as two writes on the memory
  | side.

Just restating what you're writing (as I don't know x86 hardware, or for that
matter, any modern hardware, at all) ...

But might the issue be successive writes to the same location - I can imagine
that some "smart" processor, without some kind of barrier inserted bwtewwn,
might optimise out the first one as being useless - which in regular RAM it
would be, but not when the destination is a device register.

kre