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Re: New Dell Optiplex 990 Network card problem
The content type of my last .dif file was video/x-dv...
So, I resend it.
(2011/05/13 16:17), Phil Nelson wrote:
> On Friday 13 May 2011 12:24:23 pm SAITOH Masanobu wrote:
>> I'm now writing the patch.
>>
>
> Thanks much. I'll check it out.
>
> --Phil
>
>
--
-----------------------------------------------
SAITOH Masanobu (msaitoh%execsw.org@localhost
msaitoh%netbsd.org@localhost)
Index: if_wmreg.h
===================================================================
RCS file: /cvsroot/src/sys/dev/pci/if_wmreg.h,v
retrieving revision 1.44
diff -u -r1.44 if_wmreg.h
--- if_wmreg.h 14 Jul 2010 00:11:06 -0000 1.44
+++ if_wmreg.h 13 May 2011 18:19:51 -0000
@@ -675,6 +675,7 @@
#define PBA_20K 0x0014
#define PBA_22K 0x0016
#define PBA_24K 0x0018
+#define PBA_26K 0x001a
#define PBA_30K 0x001e
#define PBA_32K 0x0020
#define PBA_35K 0x0023
Index: if_wmvar.h
===================================================================
RCS file: /cvsroot/src/sys/dev/pci/if_wmvar.h,v
retrieving revision 1.11
diff -u -r1.11 if_wmvar.h
--- if_wmvar.h 7 Mar 2010 09:05:19 -0000 1.11
+++ if_wmvar.h 13 May 2011 18:19:51 -0000
@@ -123,6 +123,7 @@
WM_T_ICH9, /* ICH9 LAN */
WM_T_ICH10, /* ICH10 LAN */
WM_T_PCH, /* PCH LAN */
+ WM_T_PCH2, /* PCH2 LAN */
} wm_chip_type;
typedef enum {
Index: if_wm.c
===================================================================
RCS file: /cvsroot/src/sys/dev/pci/if_wm.c,v
retrieving revision 1.220
diff -u -r1.220 if_wm.c
--- if_wm.c 22 Feb 2011 21:19:30 -0000 1.220
+++ if_wm.c 13 May 2011 18:19:53 -0000
@@ -921,6 +921,12 @@
WM_T_PCH, WMP_F_1000T },
{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PCH_D_DC,
"PCH LAN (82578DC) Controller",
+ WM_T_PCH2, WMP_F_1000T },
+ { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PCH2_LV_LM,
+ "PCH2 LAN (82579LM) Controller",
+ WM_T_PCH2, WMP_F_1000T },
+ { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PCH2_LV_V,
+ "PCH2 LAN (82579V) Controller",
WM_T_PCH, WMP_F_1000T },
{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82575EB_COPPER,
"82575EB dual-1000baseT Ethernet",
@@ -1284,9 +1290,10 @@
sc->sc_flags |= WM_F_PCIE;
if ((sc->sc_type != WM_T_ICH8) && (sc->sc_type != WM_T_ICH9)
&& (sc->sc_type != WM_T_ICH10)
- && (sc->sc_type != WM_T_PCH)) {
+ && (sc->sc_type != WM_T_PCH)
+ && (sc->sc_type != WM_T_PCH2)) {
sc->sc_flags |= WM_F_EEPROM_SEMAPHORE;
- /* ICH* and PCH have no PCIe capability registers */
+ /* ICH* and PCH* have no PCIe capability registers */
if (pci_get_capability(pa->pa_pc, pa->pa_tag,
PCI_CAP_PCIEXPRESS, &sc->sc_pcixe_capoff,
NULL) == 0)
@@ -1468,6 +1475,7 @@
case WM_T_ICH9:
case WM_T_ICH10:
case WM_T_PCH:
+ case WM_T_PCH2:
if (wm_check_mng_mode(sc) != 0)
wm_get_hw_control(sc);
break;
@@ -1542,6 +1550,7 @@
case WM_T_ICH9:
case WM_T_ICH10:
case WM_T_PCH:
+ case WM_T_PCH2: /* XXX */
/* FLASH */
sc->sc_flags |= WM_F_EEPROM_FLASH | WM_F_SWFWHW_SYNC;
memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, WM_ICH8_FLASH);
@@ -1681,6 +1690,7 @@
case WM_T_ICH9:
case WM_T_ICH10:
case WM_T_PCH:
+ case WM_T_PCH2:
apme_mask = WUC_APME;
eeprom_data = CSR_READ(sc, WMREG_WUC);
break;
@@ -1782,7 +1792,7 @@
*/
if (sc->sc_type == WM_T_ICH8 || sc->sc_type == WM_T_ICH9
|| sc->sc_type == WM_T_ICH10 || sc->sc_type == WM_T_PCH
- || sc->sc_type == WM_T_82573
+ || sc->sc_type == WM_T_PCH2 || sc->sc_type == WM_T_82573
|| sc->sc_type == WM_T_82574 || sc->sc_type == WM_T_82583) {
/* STATUS_TBIMODE reserved/reused, can't rely on it */
wm_gmii_mediainit(sc, wmp->wmp_product);
@@ -1861,6 +1871,7 @@
case WM_T_80003:
case WM_T_ICH9:
case WM_T_ICH10:
+ case WM_T_PCH2: /* PCH2 supports 9K frame size */
/* XXX limited to 9234 */
sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU;
break;
@@ -3438,8 +3449,10 @@
break;
case WM_T_ICH9:
case WM_T_ICH10:
- case WM_T_PCH:
sc->sc_pba = PBA_10K;
+ case WM_T_PCH:
+ case WM_T_PCH2:
+ sc->sc_pba = PBA_26K;
break;
default:
sc->sc_pba = sc->sc_ethercom.ec_if.if_mtu > 8192 ?
@@ -3550,6 +3563,7 @@
case WM_T_ICH9:
case WM_T_ICH10:
case WM_T_PCH:
+ case WM_T_PCH2: /* XXX */
reg = CSR_READ(sc, WMREG_CTRL) | CTRL_RST;
if (wm_check_reset_block(sc) == 0) {
if (sc->sc_type >= WM_T_PCH) {
@@ -3650,6 +3664,7 @@
break;
case WM_T_ICH10:
case WM_T_PCH:
+ case WM_T_PCH2:
wm_lan_init_done(sc);
break;
default:
@@ -3776,6 +3791,7 @@
case WM_T_ICH9:
case WM_T_ICH10:
case WM_T_PCH:
+ case WM_T_PCH2: /* XXX */
if (wm_check_mng_mode(sc) != 0)
wm_get_hw_control(sc);
break;
@@ -3919,7 +3935,8 @@
* XXX Values could probably stand some tuning.
*/
if ((sc->sc_type != WM_T_ICH8) && (sc->sc_type != WM_T_ICH9)
- && (sc->sc_type != WM_T_ICH10) && (sc->sc_type != WM_T_PCH)) {
+ && (sc->sc_type != WM_T_ICH10) && (sc->sc_type != WM_T_PCH)
+ && (sc->sc_type != WM_T_PCH2)) {
CSR_WRITE(sc, WMREG_FCAL, FCAL_CONST);
CSR_WRITE(sc, WMREG_FCAH, FCAH_CONST);
CSR_WRITE(sc, WMREG_FCT, ETHERTYPE_FLOWCONTROL);
@@ -3951,6 +3968,7 @@
case WM_T_ICH9:
case WM_T_ICH10:
case WM_T_PCH:
+ case WM_T_PCH2: /* XXX */
/*
* Set the mac to wait the maximum time between each
* iteration and increase the max iterations when
@@ -4014,7 +4032,8 @@
CSR_WRITE(sc, WMREG_IMS, sc->sc_icr);
if ((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9)
- || (sc->sc_type == WM_T_ICH10) || (sc->sc_type == WM_T_PCH)) {
+ || (sc->sc_type == WM_T_ICH10) || (sc->sc_type == WM_T_PCH)
+ || (sc->sc_type == WM_T_PCH2)) {
reg = CSR_READ(sc, WMREG_KABGTXD);
reg |= KABGTXD_BGSQLBIAS;
CSR_WRITE(sc, WMREG_KABGTXD, reg);
@@ -4279,6 +4298,7 @@
switch (sc->sc_type) {
case WM_T_ICH10:
case WM_T_PCH:
+ case WM_T_PCH2: /* XXX */
for (i = 0; i < WM_ICH8_LAN_INIT_TIMEOUT; i++) {
reg = CSR_READ(sc, WMREG_STATUS);
if ((reg & STATUS_LAN_INIT_DONE) != 0)
@@ -4356,6 +4376,7 @@
case WM_T_ICH9:
case WM_T_ICH10:
case WM_T_PCH:
+ case WM_T_PCH2: /* XXX */
if (sc->sc_type >= WM_T_PCH) {
reg = CSR_READ(sc, WMREG_STATUS);
if ((reg & STATUS_PHYRA) != 0)
@@ -4670,7 +4691,8 @@
return 1;
if ((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9)
- || (sc->sc_type == WM_T_ICH10) || (sc->sc_type == WM_T_PCH))
+ || (sc->sc_type == WM_T_ICH10) || (sc->sc_type == WM_T_PCH)
+ || (sc->sc_type == WM_T_PCH2))
rv = wm_read_eeprom_ich8(sc, word, wordcnt, data);
else if (sc->sc_flags & WM_F_EEPROM_EERDEEWR)
rv = wm_read_eeprom_eerd(sc, word, wordcnt, data);
@@ -4946,7 +4968,8 @@
uint32_t hash;
if ((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9)
- || (sc->sc_type == WM_T_ICH10) || (sc->sc_type == WM_T_PCH)) {
+ || (sc->sc_type == WM_T_ICH10) || (sc->sc_type == WM_T_PCH)
+ || (sc->sc_type == WM_T_PCH2)) {
hash = (enaddr[4] >> ich8_lo_shift[sc->sc_mchash_type]) |
(((uint16_t) enaddr[5]) <<
ich8_hi_shift[sc->sc_mchash_type]);
return (hash & 0x3ff);
@@ -4992,7 +5015,8 @@
* clear the remaining slots.
*/
if ((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9)
- || (sc->sc_type == WM_T_ICH10) || (sc->sc_type == WM_T_PCH))
+ || (sc->sc_type == WM_T_ICH10) || (sc->sc_type == WM_T_PCH)
+ || (sc->sc_type == WM_T_PCH2))
size = WM_ICH8_RAL_TABSIZE;
else
size = WM_RAL_TABSIZE;
@@ -5001,7 +5025,8 @@
wm_set_ral(sc, NULL, i);
if ((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9)
- || (sc->sc_type == WM_T_ICH10) || (sc->sc_type == WM_T_PCH))
+ || (sc->sc_type == WM_T_ICH10) || (sc->sc_type == WM_T_PCH)
+ || (sc->sc_type == WM_T_PCH2))
size = WM_ICH8_MC_TABSIZE;
else
size = WM_MC_TABSIZE;
@@ -5027,7 +5052,8 @@
reg = (hash >> 5);
if ((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9)
- || (sc->sc_type == WM_T_ICH10) || (sc->sc_type == WM_T_PCH))
+ || (sc->sc_type == WM_T_ICH10) || (sc->sc_type == WM_T_PCH)
+ || (sc->sc_type == WM_T_PCH2))
reg &= 0x1f;
else
reg &= 0x7f;
@@ -5376,6 +5402,7 @@
case WM_T_ICH9:
case WM_T_ICH10:
case WM_T_PCH:
+ case WM_T_PCH2: /* XXX */
rv = wm_get_swfwhw_semaphore(sc);
break;
default:
@@ -5458,6 +5485,7 @@
case WM_T_ICH9:
case WM_T_ICH10:
case WM_T_PCH:
+ case WM_T_PCH2: /* XXX */
/* generic reset */
CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl | CTRL_PHY_RESET);
delay(100);
@@ -5491,6 +5519,7 @@
case WM_T_ICH9:
case WM_T_ICH10:
case WM_T_PCH:
+ case WM_T_PCH2: /* XXX */
wm_put_swfwhw_semaphore(sc);
break;
default:
@@ -5535,6 +5564,7 @@
case WM_T_ICH9:
case WM_T_ICH10:
case WM_T_PCH:
+ case WM_T_PCH2: /* XXX */
/* Allow time for h/w to get to a quiescent state afer reset */
delay(10*1000);
@@ -6922,6 +6952,7 @@
case WM_T_ICH9:
case WM_T_ICH10:
case WM_T_PCH:
+ case WM_T_PCH2: /* XXX */
rv = wm_check_mng_mode_ich8lan(sc);
break;
case WM_T_82574:
@@ -7022,6 +7053,7 @@
case WM_T_ICH9:
case WM_T_ICH10:
case WM_T_PCH:
+ case WM_T_PCH2: /* XXX */
reg = CSR_READ(sc, WMREG_FWSM);
if ((reg & FWSM_RSPCIPHY) != 0)
return 0;
@@ -7067,6 +7099,7 @@
case WM_T_ICH9:
case WM_T_ICH10:
case WM_T_PCH:
+ case WM_T_PCH2: /* XXX */
reg = CSR_READ(sc, WMREG_CTRL_EXT);
CSR_WRITE(sc, WMREG_CTRL_EXT, reg | CTRL_EXT_DRV_LOAD);
break;
@@ -7486,6 +7519,7 @@
case WM_T_ICH9:
case WM_T_ICH10:
case WM_T_PCH:
+ case WM_T_PCH2: /* XXX */
sc->sc_flags |= WM_F_HAS_AMT;
sc->sc_flags |= WM_F_ASF_FIRMWARE_PRES;
break;
@@ -7560,6 +7594,7 @@
case WM_T_ICH9:
case WM_T_ICH10:
case WM_T_PCH:
+ case WM_T_PCH2: /* XXX */
/* Disable gig during WOL */
reg = CSR_READ(sc, WMREG_PHY_CTRL);
reg |= PHY_CTRL_D0A_LPLU | PHY_CTRL_GBE_DIS;
@@ -7604,7 +7639,8 @@
}
if (((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9)
- || (sc->sc_type == WM_T_ICH10) || (sc->sc_type == WM_T_PCH))
+ || (sc->sc_type == WM_T_ICH10) || (sc->sc_type == WM_T_PCH)
+ || (sc->sc_type == WM_T_PCH2))
&& (sc->sc_phytype == WMPHY_IGP_3))
wm_igp3_phy_powerdown_workaround_ich8lan(sc);
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