Re: -current on OPENRD doesn't boot

[SAITOH Masanobu <msaitoh%execsw.org@localhost>]

Hi, Sebastien.

> I rebuilt a new kernel with latest netbsd-6 sources and everything seems to be
> running fine now. At least, my OpenRD now boots correctly and dmesg shows that
> my SATA disk is wd0 :) !

 good!

> I'm not sure whether last time error was due to a bug in NetBSD sources or if 
> I
> messed up while "patching" and updating the sources.
> 
> I indeed need to comment the following line from sys/dev/marvell/if_mvgbe.c
> (mvgbe_ports array):
> 
>   { MARVELL_KIRKWOOD_88F6281,     1, 1, { 15 }, FLAGS_FIX_TQTB },
> 
> because my OpenRD-Base only has _one_ Gb ethernet port, and NetBSD was stuck 
> in
> the boot process for seeking a second one (well, that's my understanding...).
> 
> So I might have messed up with cvs updates that followed. Sorry !
> 
> Thank you,
> 
> Sebastien

 Could you test with the following patch? I suspect your borard's 2nd internal
Ethernel MAC is disabled using the clock gating function and being hanging
to access a regsiter in the device.


Index: mvsoc.c
===================================================================
RCS file: /cvsroot/src/sys/arch/arm/marvell/mvsoc.c,v
retrieving revision 1.9
diff -u -r1.9 mvsoc.c
--- mvsoc.c     10 Aug 2012 02:18:20 -0000      1.9
+++ mvsoc.c     17 Oct 2012 18:26:50 -0000
@@ -252,6 +252,7 @@
        int unit;
        bus_size_t offset;
        int irq;
+       uint32_t clkpwr_bit;
 } mvsoc_periphs[] = {
 #if defined(ORION)
     { ORION_1(88F1181),        "mvsoctmr",0, MVSOC_TMR_BASE,   IRQ_DEFAULT },
@@ -392,15 +393,23 @@
     { KIRKWOOD(88F6281),"mvsocrtc",0, KIRKWOOD_RTC_BASE,IRQ_DEFAULT },
     { KIRKWOOD(88F6281),"com",     0, MVSOC_COM0_BASE, KIRKWOOD_IRQ_UART0INT },
     { KIRKWOOD(88F6281),"com",     1, MVSOC_COM1_BASE, KIRKWOOD_IRQ_UART1INT },
-    { KIRKWOOD(88F6281),"ehci",    0, KIRKWOOD_USB_BASE,KIRKWOOD_IRQ_USB0CNT },
+    { KIRKWOOD(88F6281),"ehci",    0, KIRKWOOD_USB_BASE,KIRKWOOD_IRQ_USB0CNT,
+                                       MVSOC_MLMB_CLKGATING_BIT(3) },
     { KIRKWOOD(88F6281),"gtidmac", 0, KIRKWOOD_IDMAC_BASE,IRQ_DEFAULT },
     { KIRKWOOD(88F6281),"gttwsi",  0, MVSOC_TWSI_BASE, KIRKWOOD_IRQ_TWSI },
-    { KIRKWOOD(88F6281),"mvcesa",  0, 
KIRKWOOD_CESA_BASE,KIRKWOOD_IRQ_SECURITYINT},
-    { KIRKWOOD(88F6281),"mvgbec",  0, KIRKWOOD_GBE0_BASE,IRQ_DEFAULT },
-    { KIRKWOOD(88F6281),"mvgbec",  1, KIRKWOOD_GBE1_BASE,IRQ_DEFAULT },
-    { KIRKWOOD(88F6281),"mvpex",   0, MVSOC_PEX_BASE,  KIRKWOOD_IRQ_PEX0INT },
-    { KIRKWOOD(88F6281),"mvsata",  0, KIRKWOOD_SATAHC_BASE,KIRKWOOD_IRQ_SATA },
-    { KIRKWOOD(88F6281),"mvsdio",  0, KIRKWOOD_SDIO_BASE,KIRKWOOD_IRQ_SDIOINT 
},
+    { KIRKWOOD(88F6281),"mvcesa",  0, 
KIRKWOOD_CESA_BASE,KIRKWOOD_IRQ_SECURITYINT,
+                                       MVSOC_MLMB_CLKGATING_BIT(17) },
+    { KIRKWOOD(88F6281),"mvgbec",  0, KIRKWOOD_GBE0_BASE,IRQ_DEFAULT,
+                                       MVSOC_MLMB_CLKGATING_BIT(0) },
+    { KIRKWOOD(88F6281),"mvgbec",  1, KIRKWOOD_GBE1_BASE,IRQ_DEFAULT,
+                                       MVSOC_MLMB_CLKGATING_BIT(19) },
+    { KIRKWOOD(88F6281),"mvpex",   0, MVSOC_PEX_BASE,  KIRKWOOD_IRQ_PEX0INT,
+                                       MVSOC_MLMB_CLKGATING_BIT(2) },
+    { KIRKWOOD(88F6281),"mvsata",  0, KIRKWOOD_SATAHC_BASE,KIRKWOOD_IRQ_SATA,
+                                       MVSOC_MLMB_CLKGATING_BIT(14) |
+                                       MVSOC_MLMB_CLKGATING_BIT(15) },
+    { KIRKWOOD(88F6281),"mvsdio",  0, KIRKWOOD_SDIO_BASE,KIRKWOOD_IRQ_SDIOINT,
+                                       MVSOC_MLMB_CLKGATING_BIT(4) },

     { KIRKWOOD(88F6282),"mvsoctmr",0, MVSOC_TMR_BASE,  IRQ_DEFAULT },
     { KIRKWOOD(88F6282),"mvsocgpp",0, MVSOC_GPP_BASE,  KIRKWOOD_IRQ_GPIOLO7_0},
@@ -458,6 +467,7 @@
        struct marvell_attach_args mva;
        uint16_t model;
        uint8_t rev;
+       uint32_t clkpwr, clkpwrbit;
        int i;

        sc->sc_dev = self;
@@ -497,6 +507,20 @@
                if (mvsoc_periphs[i].model != model)
                        continue;

+               /* Skip clock disabled devices */
+               clkpwrbit = mvsoc_periphs[i].clkpwr_bit;
+               if (clkpwrbit != 0) {
+                       clkpwr = read_mlmbreg(MVSOC_MLMB_CLKGATING);
+
+                       if ((clkpwr & clkpwrbit) == 0) {
+                               aprint_normal("%s: %s%d clock disabled\n",
+                                   device_xname(self),
+                                   mvsoc_periphs[i].name,
+                                   mvsoc_periphs[i].unit);
+                               continue;
+                       }
+               }
+
                mva.mva_name = mvsoc_periphs[i].name;
                mva.mva_model = model;
                mva.mva_revision = rev;
Index: mvsocreg.h
===================================================================
RCS file: /cvsroot/src/sys/arch/arm/marvell/mvsocreg.h,v
retrieving revision 1.2
diff -u -r1.2 mvsocreg.h
--- mvsocreg.h  1 Feb 2011 22:54:24 -0000       1.2
+++ mvsocreg.h  17 Oct 2012 18:26:50 -0000
@@ -110,6 +110,9 @@
 #define MVSOC_MLMB_MLMBICR               0x110 /*Mb-L to Mb Bridge Intr Cause*/
 #define MVSOC_MLMB_MLMBIMR               0x114 /*Mb-L to Mb Bridge Intr Mask */

+#define MVSOC_MLMB_CLKGATING             0x11c /* Clock Gating Control */
+#define MVSOC_MLMB_CLKGATING_BIT(n)      (1 << (n))
+
 #define MVSOC_MLMB_L2CFG                 0x128 /* L2 Cache Config */

 #define MVSOC_TMR_BASE                 (MVSOC_MLMB_BASE + 0x0300)


-- 
-----------------------------------------------
                SAITOH Masanobu (msaitoh%execsw.org@localhost
                                 msaitoh%netbsd.org@localhost)