Re: TS-7200: time sync issues

[Ken Hornstein <kenh%cmf.nrl.navy.mil@localhost>]

>Those bus cycles should be approximately 320 nS each.  The RTC has no 
>connection to the processor WAIT# signal so its not possible for it to 
>extend bus cycles.  That UIP bit will be set some ?? uS before a once 
>per second update.  As long as you have a functioning battery-backed RTC 
>(TS-5620) on the PC104 bus, that UIP should only be set for a very short 
>time that should be of no consequence. 

Of course I bow to your obvious greater hardware experience, especially
since you work for the company that designed this board :-) (from what
I read on the DS1687 datasheet, the UIP bit is set 244 us before the
update cycle starts).  So that doesn't SEEM like it should matter.

Waitaminute ... you want to do the update when UIP is NOT set, right?
Then isn't this test backwards?

tight loop at splclock() {
        if ((*sc->sc_mcread)(sc, MC_REGA) & MC_REGA_UIP)
                break;
}

Wouldn't you want to break this loop and set the time when UIP bit is
low?  Or is the idea to set the time right before the update cycle
starts?  I admit I'm a bit confused here.

--Ken