Re: kern/57515: sparc32 GCC defaults to SC memory ordering, which is not true on SPARCv8 processors

[Koakuma <koachan+netbsd%protonmail.com@localhost>]

The following reply was made to PR port-sparc/57515; it has been noted by GNATS.

From: Koakuma <koachan+netbsd%protonmail.com@localhost>
To: gnats-bugs%netbsd.org@localhost
Cc: port-sparc-maintainer%netbsd.org@localhost, gnats-admin%netbsd.org@localhost, netbsd-bugs%netbsd.org@localhost
Subject: Re: kern/57515: sparc32 GCC defaults to SC memory ordering, which is not true on SPARCv8 processors
Date: Sun, 09 Jul 2023 02:17:25 +0000

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 Martin Husemann wrote:
 > Well, I don't know about v8 and early details, but kinda assumed it
 > would be similar to v9 where it is under (kernel's) software controll
 > (and binaries get run with the memory model they are compiled for).
 
 Even if it works that way, v8 and v9 does not have sequential consistency
 as a supported memory model, so binaries targeted for v7 might still run
 wrongly on later processors anyway.
 
 Taylor R Campbell wrote:
 > That's an option too, but I bet it could be made to work reasonably
 > well with a small tweak to gcc so that NetBSD can ask for -mcpu=3Dv7
 > -mmemory-model=3Dtso instead of having -mcpu=3Dv7 ignore -mmemory-model,
 > if someone is willing to do the work and testing for it.
 
 I just made this small patch that removes all the conditionals for
 barrier instructions (except for `stbar` and `membar` since those are
 not available in v7) and changes the default memory ordering to TSO.
 Seems to get it to emit the proper barriers for me, but probably could
 be done a little bit better, since I am not familiar with GCC internals.
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